[llvm] r304246 - MIR: remove explicit "noVRegs" property.
Tim Northover via llvm-commits
llvm-commits at lists.llvm.org
Tue May 30 14:28:58 PDT 2017
Author: tnorthover
Date: Tue May 30 16:28:57 2017
New Revision: 304246
URL: http://llvm.org/viewvc/llvm-project?rev=304246&view=rev
Log:
MIR: remove explicit "noVRegs" property.
We can infer this from the incoming MIR, so there's no reason to
represent it with a special flag.
Modified:
llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
llvm/trunk/lib/CodeGen/MIRPrinter.cpp
llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir
llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir
llvm/trunk/test/CodeGen/Thumb2/tbb-removeadd.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir
Modified: llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h (original)
+++ llvm/trunk/include/llvm/CodeGen/MIRYamlMapping.h Tue May 30 16:28:57 2017
@@ -381,7 +381,6 @@ struct MachineFunction {
StringRef Name;
unsigned Alignment = 0;
bool ExposesReturnsTwice = false;
- bool NoVRegs;
// GISel MachineFunctionProperties.
bool Legalized = false;
bool RegBankSelected = false;
@@ -406,7 +405,6 @@ template <> struct MappingTraits<Machine
YamlIO.mapRequired("name", MF.Name);
YamlIO.mapOptional("alignment", MF.Alignment);
YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
- YamlIO.mapOptional("noVRegs", MF.NoVRegs);
YamlIO.mapOptional("legalized", MF.Legalized);
YamlIO.mapOptional("regBankSelected", MF.RegBankSelected);
YamlIO.mapOptional("selected", MF.Selected);
Modified: llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRParser/MIRParser.cpp Tue May 30 16:28:57 2017
@@ -332,8 +332,6 @@ bool MIRParserImpl::initializeMachineFun
MF.setAlignment(YamlMF.Alignment);
MF.setExposesReturnsTwice(YamlMF.ExposesReturnsTwice);
- if (YamlMF.NoVRegs)
- MF.getProperties().set(MachineFunctionProperties::Property::NoVRegs);
if (YamlMF.Legalized)
MF.getProperties().set(MachineFunctionProperties::Property::Legalized);
if (YamlMF.RegBankSelected)
Modified: llvm/trunk/lib/CodeGen/MIRPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/MIRPrinter.cpp?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/MIRPrinter.cpp (original)
+++ llvm/trunk/lib/CodeGen/MIRPrinter.cpp Tue May 30 16:28:57 2017
@@ -183,8 +183,6 @@ void MIRPrinter::print(const MachineFunc
YamlMF.Alignment = MF.getAlignment();
YamlMF.ExposesReturnsTwice = MF.exposesReturnsTwice();
- YamlMF.NoVRegs = MF.getProperties().hasProperty(
- MachineFunctionProperties::Property::NoVRegs);
YamlMF.Legalized = MF.getProperties().hasProperty(
MachineFunctionProperties::Property::Legalized);
YamlMF.RegBankSelected = MF.getProperties().hasProperty(
Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/select-pr32733.mir Tue May 30 16:28:57 2017
@@ -13,7 +13,6 @@
name: main
alignment: 2
exposesReturnsTwice: false
-noVRegs: false
legalized: true
regBankSelected: true
selected: false
Modified: llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/merge-m0.mir Tue May 30 16:28:57 2017
@@ -50,7 +50,6 @@
name: test
alignment: 0
exposesReturnsTwice: false
-noVRegs: false
legalized: false
regBankSelected: false
selected: false
Modified: llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/v6-jumptable-clobber.mir Tue May 30 16:28:57 2017
@@ -190,7 +190,6 @@
name: foo
alignment: 1
exposesReturnsTwice: false
-noVRegs: true
legalized: false
regBankSelected: false
selected: false
@@ -289,7 +288,6 @@ body: |
name: bar
alignment: 1
exposesReturnsTwice: false
-noVRegs: true
legalized: false
regBankSelected: false
selected: false
Modified: llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir (original)
+++ llvm/trunk/test/CodeGen/Mips/compactbranches/empty-block.mir Tue May 30 16:28:57 2017
@@ -39,7 +39,6 @@
name: l5
alignment: 2
exposesReturnsTwice: false
-noVRegs: true
legalized: false
regBankSelected: false
selected: false
Modified: llvm/trunk/test/CodeGen/Thumb2/tbb-removeadd.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Thumb2/tbb-removeadd.mir?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Thumb2/tbb-removeadd.mir (original)
+++ llvm/trunk/test/CodeGen/Thumb2/tbb-removeadd.mir Tue May 30 16:28:57 2017
@@ -39,7 +39,6 @@
name: Func
alignment: 1
exposesReturnsTwice: false
-noVRegs: true
legalized: false
regBankSelected: false
selected: false
Modified: llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/irtranslator-call.ll Tue May 30 16:28:57 2017
@@ -5,7 +5,6 @@ define void @test_void_return() {
; CHECK-LABEL: name: test_void_return
; CHECK: alignment: 4
; CHECK-NEXT: exposesReturnsTwice: false
-; CHECK-NEXT: noVRegs: false
; CHECK-NEXT: legalized: false
; CHECK-NEXT: regBankSelected: false
; CHECK-NEXT: selected: false
Modified: llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir?rev=304246&r1=304245&r2=304246&view=diff
==============================================================================
--- llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir (original)
+++ llvm/trunk/test/DebugInfo/MIR/X86/empty-inline.mir Tue May 30 16:28:57 2017
@@ -73,7 +73,6 @@
name: _ZN1C5m_fn3Ev
alignment: 4
exposesReturnsTwice: false
-noVRegs: true
legalized: false
regBankSelected: false
selected: false
More information about the llvm-commits
mailing list