[llvm] r304121 - Revert "[X86] Adding new LLVM TableGen backend that generates the X86 backend memory folding tables."
Zachary Turner via llvm-commits
llvm-commits at lists.llvm.org
Sun May 28 19:20:47 PDT 2017
Resubmitted in r304122, with the fix in r304123
On Sun, May 28, 2017 at 7:12 PM Zachary Turner <zturner at google.com> wrote:
> So it turns out this was pretty easy to fix, guess I should have dug in
> earlier before reverting. I'll push a fixed version of the patch.
>
> On Sun, May 28, 2017 at 7:01 PM Zachary Turner <zturner at google.com> wrote:
>
>> The builders are showing it, but they're not symbolized. I'll go back to
>> an earlier revision locally and see if I can get you something more useful.
>>
>> On Sun, May 28, 2017 at 6:56 PM Craig Topper <craig.topper at gmail.com>
>> wrote:
>>
>>> Do you have the segfault link? I commited a fix for the one I saw
>>> earlier. Would like to see if it continued after that fix.
>>>
>>> ~Craig
>>>
>>> On Sun, May 28, 2017 at 6:48 PM, Zachary Turner via llvm-commits <
>>> llvm-commits at lists.llvm.org> wrote:
>>>
>>>> Author: zturner
>>>> Date: Sun May 28 20:48:53 2017
>>>> New Revision: 304121
>>>>
>>>> URL: http://llvm.org/viewvc/llvm-project?rev=304121&view=rev
>>>> Log:
>>>> Revert "[X86] Adding new LLVM TableGen backend that generates the X86
>>>> backend memory folding tables."
>>>>
>>>> This reverts commit 28cb1003507f287726f43c771024a1dc102c45fe as well
>>>> as all subsequent followups. llvm-tblgen currently segfaults with
>>>> this change, and it seems it has been broken on the bots all
>>>> day with no fixes in preparation. See, for example:
>>>>
>>>> http://lab.llvm.org:8011/builders/clang-x86-windows-msvc2015/
>>>>
>>>> Removed:
>>>> llvm/trunk/utils/TableGen/X86FoldTablesEmitter.cpp
>>>> Modified:
>>>> llvm/trunk/lib/Target/X86/CMakeLists.txt
>>>> llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
>>>> llvm/trunk/test/CodeGen/X86/sse42-intrinsics-fast-isel.ll
>>>> llvm/trunk/test/CodeGen/X86/stack-folding-fp-avx1.ll
>>>> llvm/trunk/test/CodeGen/X86/vector-sqrt.ll
>>>> llvm/trunk/utils/TableGen/CMakeLists.txt
>>>> llvm/trunk/utils/TableGen/TableGen.cpp
>>>> llvm/trunk/utils/TableGen/TableGenBackends.h
>>>>
>>>> Modified: llvm/trunk/lib/Target/X86/CMakeLists.txt
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/CMakeLists.txt?rev=304121&r1=304120&r2=304121&view=diff
>>>>
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/X86/CMakeLists.txt (original)
>>>> +++ llvm/trunk/lib/Target/X86/CMakeLists.txt Sun May 28 20:48:53 2017
>>>> @@ -11,7 +11,6 @@ tablegen(LLVM X86GenFastISel.inc -gen-fa
>>>> tablegen(LLVM X86GenCallingConv.inc -gen-callingconv)
>>>> tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget)
>>>> tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables)
>>>> -tablegen(LLVM X86GenFoldTables.inc -gen-x86-fold-tables)
>>>> if(LLVM_BUILD_GLOBAL_ISEL)
>>>> tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank)
>>>> tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel)
>>>>
>>>> Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
>>>> URL:
>>>> http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=304121&r1=304120&r2=304121&view=diff
>>>>
>>>> ==============================================================================
>>>> --- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
>>>> +++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Sun May 28 20:48:53 2017
>>>> @@ -121,8 +121,172 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
>>>> (STI.is64Bit() ? X86::RETQ : X86::RETL)),
>>>> Subtarget(STI), RI(STI.getTargetTriple()) {
>>>>
>>>> -// Generated memory folding tables.
>>>> -#include "X86GenFoldTables.inc"
>>>> + static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
>>>> + { X86::ADC32ri, X86::ADC32mi, 0 },
>>>> + { X86::ADC32ri8, X86::ADC32mi8, 0 },
>>>> + { X86::ADC32rr, X86::ADC32mr, 0 },
>>>> + { X86::ADC64ri32, X86::ADC64mi32, 0 },
>>>> + { X86::ADC64ri8, X86::ADC64mi8, 0 },
>>>> + { X86::ADC64rr, X86::ADC64mr, 0 },
>>>> + { X86::ADD16ri, X86::ADD16mi, 0 },
>>>> + { X86::ADD16ri8, X86::ADD16mi8, 0 },
>>>> + { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
>>>> + { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
>>>> + { X86::ADD16rr, X86::ADD16mr, 0 },
>>>> + { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
>>>> + { X86::ADD32ri, X86::ADD32mi, 0 },
>>>> + { X86::ADD32ri8, X86::ADD32mi8, 0 },
>>>> + { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
>>>> + { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
>>>> + { X86::ADD32rr, X86::ADD32mr, 0 },
>>>> + { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
>>>> + { X86::ADD64ri32, X86::ADD64mi32, 0 },
>>>> + { X86::ADD64ri8, X86::ADD64mi8, 0 },
>>>> + { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
>>>> + { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
>>>> + { X86::ADD64rr, X86::ADD64mr, 0 },
>>>> + { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
>>>> + { X86::ADD8ri, X86::ADD8mi, 0 },
>>>> + { X86::ADD8rr, X86::ADD8mr, 0 },
>>>> + { X86::AND16ri, X86::AND16mi, 0 },
>>>> + { X86::AND16ri8, X86::AND16mi8, 0 },
>>>> + { X86::AND16rr, X86::AND16mr, 0 },
>>>> + { X86::AND32ri, X86::AND32mi, 0 },
>>>> + { X86::AND32ri8, X86::AND32mi8, 0 },
>>>> + { X86::AND32rr, X86::AND32mr, 0 },
>>>> + { X86::AND64ri32, X86::AND64mi32, 0 },
>>>> + { X86::AND64ri8, X86::AND64mi8, 0 },
>>>> + { X86::AND64rr, X86::AND64mr, 0 },
>>>> + { X86::AND8ri, X86::AND8mi, 0 },
>>>> + { X86::AND8rr, X86::AND8mr, 0 },
>>>> + { X86::DEC16r, X86::DEC16m, 0 },
>>>> + { X86::DEC32r, X86::DEC32m, 0 },
>>>> + { X86::DEC64r, X86::DEC64m, 0 },
>>>> + { X86::DEC8r, X86::DEC8m, 0 },
>>>> + { X86::INC16r, X86::INC16m, 0 },
>>>> + { X86::INC32r, X86::INC32m, 0 },
>>>> + { X86::INC64r, X86::INC64m, 0 },
>>>> + { X86::INC8r, X86::INC8m, 0 },
>>>> + { X86::NEG16r, X86::NEG16m, 0 },
>>>> + { X86::NEG32r, X86::NEG32m, 0 },
>>>> + { X86::NEG64r, X86::NEG64m, 0 },
>>>> + { X86::NEG8r, X86::NEG8m, 0 },
>>>> + { X86::NOT16r, X86::NOT16m, 0 },
>>>> + { X86::NOT32r, X86::NOT32m, 0 },
>>>> + { X86::NOT64r, X86::NOT64m, 0 },
>>>> + { X86::NOT8r, X86::NOT8m, 0 },
>>>> + { X86::OR16ri, X86::OR16mi, 0 },
>>>> + { X86::OR16ri8, X86::OR16mi8, 0 },
>>>> + { X86::OR16rr, X86::OR16mr, 0 },
>>>> + { X86::OR32ri, X86::OR32mi, 0 },
>>>> + { X86::OR32ri8, X86::OR32mi8, 0 },
>>>> + { X86::OR32rr, X86::OR32mr, 0 },
>>>> + { X86::OR64ri32, X86::OR64mi32, 0 },
>>>> + { X86::OR64ri8, X86::OR64mi8, 0 },
>>>> + { X86::OR64rr, X86::OR64mr, 0 },
>>>> + { X86::OR8ri, X86::OR8mi, 0 },
>>>> + { X86::OR8rr, X86::OR8mr, 0 },
>>>> + { X86::ROL16r1, X86::ROL16m1, 0 },
>>>> + { X86::ROL16rCL, X86::ROL16mCL, 0 },
>>>> + { X86::ROL16ri, X86::ROL16mi, 0 },
>>>> + { X86::ROL32r1, X86::ROL32m1, 0 },
>>>> + { X86::ROL32rCL, X86::ROL32mCL, 0 },
>>>> + { X86::ROL32ri, X86::ROL32mi, 0 },
>>>> + { X86::ROL64r1, X86::ROL64m1, 0 },
>>>> + { X86::ROL64rCL, X86::ROL64mCL, 0 },
>>>> + { X86::ROL64ri, X86::ROL64mi, 0 },
>>>> + { X86::ROL8r1, X86::ROL8m1, 0 },
>>>> + { X86::ROL8rCL, X86::ROL8mCL, 0 },
>>>> + { X86::ROL8ri, X86::ROL8mi, 0 },
>>>> + { X86::ROR16r1, X86::ROR16m1, 0 },
>>>> + { X86::ROR16rCL, X86::ROR16mCL, 0 },
>>>> + { X86::ROR16ri, X86::ROR16mi, 0 },
>>>> + { X86::ROR32r1, X86::ROR32m1, 0 },
>>>> + { X86::ROR32rCL, X86::ROR32mCL, 0 },
>>>> + { X86::ROR32ri, X86::ROR32mi, 0 },
>>>> + { X86::ROR64r1, X86::ROR64m1, 0 },
>>>> + { X86::ROR64rCL, X86::ROR64mCL, 0 },
>>>> + { X86::ROR64ri, X86::ROR64mi, 0 },
>>>> + { X86::ROR8r1, X86::ROR8m1, 0 },
>>>> + { X86::ROR8rCL, X86::ROR8mCL, 0 },
>>>> + { X86::ROR8ri, X86::ROR8mi, 0 },
>>>> + { X86::SAR16r1, X86::SAR16m1, 0 },
>>>> + { X86::SAR16rCL, X86::SAR16mCL, 0 },
>>>> + { X86::SAR16ri, X86::SAR16mi, 0 },
>>>> + { X86::SAR32r1, X86::SAR32m1, 0 },
>>>> + { X86::SAR32rCL, X86::SAR32mCL, 0 },
>>>> + { X86::SAR32ri, X86::SAR32mi, 0 },
>>>> + { X86::SAR64r1, X86::SAR64m1, 0 },
>>>> + { X86::SAR64rCL, X86::SAR64mCL, 0 },
>>>> + { X86::SAR64ri, X86::SAR64mi, 0 },
>>>> + { X86::SAR8r1, X86::SAR8m1, 0 },
>>>> + { X86::SAR8rCL, X86::SAR8mCL, 0 },
>>>> + { X86::SAR8ri, X86::SAR8mi, 0 },
>>>> + { X86::SBB32ri, X86::SBB32mi, 0 },
>>>> + { X86::SBB32ri8, X86::SBB32mi8, 0 },
>>>> + { X86::SBB32rr, X86::SBB32mr, 0 },
>>>> + { X86::SBB64ri32, X86::SBB64mi32, 0 },
>>>> + { X86::SBB64ri8, X86::SBB64mi8, 0 },
>>>> + { X86::SBB64rr, X86::SBB64mr, 0 },
>>>> + { X86::SHL16r1, X86::SHL16m1, 0 },
>>>> + { X86::SHL16rCL, X86::SHL16mCL, 0 },
>>>> + { X86::SHL16ri, X86::SHL16mi, 0 },
>>>> + { X86::SHL32r1, X86::SHL32m1, 0 },
>>>> + { X86::SHL32rCL, X86::SHL32mCL, 0 },
>>>> + { X86::SHL32ri, X86::SHL32mi, 0 },
>>>> + { X86::SHL64r1, X86::SHL64m1, 0 },
>>>> + { X86::SHL64rCL, X86::SHL64mCL, 0 },
>>>> + { X86::SHL64ri, X86::SHL64mi, 0 },
>>>> + { X86::SHL8r1, X86::SHL8m1, 0 },
>>>> + { X86::SHL8rCL, X86::SHL8mCL, 0 },
>>>> + { X86::SHL8ri, X86::SHL8mi, 0 },
>>>> + { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
>>>> + { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
>>>> + { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
>>>> + { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
>>>> + { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
>>>> + { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
>>>> + { X86::SHR16r1, X86::SHR16m1, 0 },
>>>> + { X86::SHR16rCL, X86::SHR16mCL, 0 },
>>>> + { X86::SHR16ri, X86::SHR16mi, 0 },
>>>> + { X86::SHR32r1, X86::SHR32m1, 0 },
>>>> + { X86::SHR32rCL, X86::SHR32mCL, 0 },
>>>> + { X86::SHR32ri, X86::SHR32mi, 0 },
>>>> + { X86::SHR64r1, X86::SHR64m1, 0 },
>>>> + { X86::SHR64rCL, X86::SHR64mCL, 0 },
>>>> + { X86::SHR64ri, X86::SHR64mi, 0 },
>>>> + { X86::SHR8r1, X86::SHR8m1, 0 },
>>>> + { X86::SHR8rCL, X86::SHR8mCL, 0 },
>>>> + { X86::SHR8ri, X86::SHR8mi, 0 },
>>>> + { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
>>>> + { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
>>>> + { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
>>>> + { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
>>>> + { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
>>>> + { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
>>>> + { X86::SUB16ri, X86::SUB16mi, 0 },
>>>> + { X86::SUB16ri8, X86::SUB16mi8, 0 },
>>>> + { X86::SUB16rr, X86::SUB16mr, 0 },
>>>> + { X86::SUB32ri, X86::SUB32mi, 0 },
>>>> + { X86::SUB32ri8, X86::SUB32mi8, 0 },
>>>> + { X86::SUB32rr, X86::SUB32mr, 0 },
>>>> + { X86::SUB64ri32, X86::SUB64mi32, 0 },
>>>> + { X86::SUB64ri8, X86::SUB64mi8, 0 },
>>>> + { X86::SUB64rr, X86::SUB64mr, 0 },
>>>> + { X86::SUB8ri, X86::SUB8mi, 0 },
>>>> + { X86::SUB8rr, X86::SUB8mr, 0 },
>>>> + { X86::XOR16ri, X86::XOR16mi, 0 },
>>>> + { X86::XOR16ri8, X86::XOR16mi8, 0 },
>>>> + { X86::XOR16rr, X86::XOR16mr, 0 },
>>>> + { X86::XOR32ri, X86::XOR32mi, 0 },
>>>> + { X86::XOR32ri8, X86::XOR32mi8, 0 },
>>>> + { X86::XOR32rr, X86::XOR32mr, 0 },
>>>> + { X86::XOR64ri32, X86::XOR64mi32, 0 },
>>>> + { X86::XOR64ri8, X86::XOR64mi8, 0 },
>>>> + { X86::XOR64rr, X86::XOR64mr, 0 },
>>>> + { X86::XOR8ri, X86::XOR8mi, 0 },
>>>> + { X86::XOR8rr, X86::XOR8mr, 0 }
>>>> + };
>>>>
>>>> for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
>>>> AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
>>>> @@ -131,11 +295,746 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
>>>> Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD |
>>>> TB_FOLDED_STORE);
>>>> }
>>>>
>>>> + static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
>>>> + { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
>>>> + { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
>>>> + { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
>>>> + { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
>>>> + { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
>>>> + { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
>>>> + { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
>>>> + { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
>>>> + { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
>>>> + { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
>>>> + { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
>>>> + { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
>>>> + { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
>>>> + { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
>>>> + { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
>>>> + { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
>>>> + { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
>>>> + { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
>>>> + { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
>>>> + { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
>>>> + { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
>>>> + { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
>>>> + { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
>>>> + { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
>>>> + { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
>>>> + { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
>>>> + { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
>>>> + { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
>>>> + { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
>>>> + { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
>>>> + { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
>>>> + { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
>>>> + { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
>>>> + { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
>>>> + { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
>>>> + { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
>>>> + { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
>>>> + { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
>>>> + { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
>>>> + { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
>>>> + { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::MOVDQUrr, X86::MOVDQUmr, TB_FOLDED_STORE },
>>>> + { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
>>>> + { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
>>>> + { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
>>>> + { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
>>>> + { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
>>>> + { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
>>>> + { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
>>>> + { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
>>>> + { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
>>>> + { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
>>>> + { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
>>>> + { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
>>>> + { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
>>>> + { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
>>>> + { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
>>>> + { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
>>>> + { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
>>>> + { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
>>>> + { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
>>>> + { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
>>>> + { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
>>>> + { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
>>>> + { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
>>>> + { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
>>>> + { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
>>>> + { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
>>>> + { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
>>>> + { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
>>>> + { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
>>>> + { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
>>>> + { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
>>>> + { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
>>>> + { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
>>>> + { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
>>>> + { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
>>>> + { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
>>>> + { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
>>>> + { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
>>>> +
>>>> + // AVX 128-bit versions of foldable instructions
>>>> + { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVDQUrr, X86::VMOVDQUmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
>>>> + { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
>>>> + { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
>>>> + { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
>>>> + { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
>>>> + { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
>>>> + { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
>>>> +
>>>> + // AVX 256-bit foldable instructions
>>>> + { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE |
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_32 },
>>>> + { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_32 },
>>>> + { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_32 },
>>>> + { X86::VMOVDQUYrr, X86::VMOVDQUYmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
>>>> +
>>>> + // AVX-512 foldable instructions
>>>> + { X86::VEXTRACTF32x4Zrr,X86::VEXTRACTF32x4Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTF32x8Zrr,X86::VEXTRACTF32x8Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTF64x2Zrr,X86::VEXTRACTF64x2Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTF64x4Zrr,X86::VEXTRACTF64x4Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTI32x4Zrr,X86::VEXTRACTI32x4Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTI32x8Zrr,X86::VEXTRACTI32x8Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTI64x2Zrr,X86::VEXTRACTI64x2Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTI64x4Zrr,X86::VEXTRACTI64x4Zmr, TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTPSZrr, X86::VEXTRACTPSZmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_64 },
>>>> + { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_64 },
>>>> + { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_64 },
>>>> + { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE |
>>>> TB_ALIGN_64 },
>>>> + { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVPQIto64Zrr, X86::VMOVPQI2QIZmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVSDto64Zrr, X86::VMOVSDto64Zmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVSS2DIZrr, X86::VMOVSS2DIZmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
>>>> + { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
>>>> + { X86::VPEXTRDZrr, X86::VPEXTRDZmr, TB_FOLDED_STORE },
>>>> + { X86::VPEXTRQZrr, X86::VPEXTRQZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVDBZrr, X86::VPMOVDBZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVDWZrr, X86::VPMOVDWZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVQDZrr, X86::VPMOVQDZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVQWZrr, X86::VPMOVQWZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVWBZrr, X86::VPMOVWBZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVSDBZrr, X86::VPMOVSDBZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVSDWZrr, X86::VPMOVSDWZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVSQDZrr, X86::VPMOVSQDZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVSQWZrr, X86::VPMOVSQWZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVSWBZrr, X86::VPMOVSWBZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVUSDBZrr, X86::VPMOVUSDBZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVUSDWZrr, X86::VPMOVUSDWZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVUSQDZrr, X86::VPMOVUSQDZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVUSQWZrr, X86::VPMOVUSQWZmr, TB_FOLDED_STORE },
>>>> + { X86::VPMOVUSWBZrr, X86::VPMOVUSWBZmr, TB_FOLDED_STORE },
>>>> +
>>>> + // AVX-512 foldable instructions (256-bit versions)
>>>> + { X86::VEXTRACTF32x4Z256rr,X86::VEXTRACTF32x4Z256mr,
>>>> TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTF64x2Z256rr,X86::VEXTRACTF64x2Z256mr,
>>>> TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTI32x4Z256rr,X86::VEXTRACTI32x4Z256mr,
>>>> TB_FOLDED_STORE },
>>>> + { X86::VEXTRACTI64x2Z256rr,X86::VEXTRACTI64x2Z256mr,
>>>> TB_FOLDED_STORE },
>>>> + { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_32 },
>>>> + { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_32 },
>>>> + { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_32 },
>>>> + { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_32 },
>>>> + { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVDWZ256rr, X86::VPMOVDWZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVQDZ256rr, X86::VPMOVQDZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVWBZ256rr, X86::VPMOVWBZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVSDWZ256rr, X86::VPMOVSDWZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVSQDZ256rr, X86::VPMOVSQDZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVSWBZ256rr, X86::VPMOVSWBZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVUSDWZ256rr, X86::VPMOVUSDWZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVUSQDZ256rr, X86::VPMOVUSQDZ256mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VPMOVUSWBZ256rr, X86::VPMOVUSWBZ256mr, TB_FOLDED_STORE
>>>> },
>>>> +
>>>> + // AVX-512 foldable instructions (128-bit versions)
>>>> + { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_16 },
>>>> + { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_16 },
>>>> + { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_16 },
>>>> + { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE
>>>> | TB_ALIGN_16 },
>>>> + { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE
>>>> },
>>>> +
>>>> + // F16C foldable instructions
>>>> + { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE
>>>> },
>>>> + { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
>>>> + };
>>>> +
>>>> for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
>>>> AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
>>>> Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
>>>> }
>>>>
>>>> + static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
>>>> + { X86::BSF16rr, X86::BSF16rm, 0 },
>>>> + { X86::BSF32rr, X86::BSF32rm, 0 },
>>>> + { X86::BSF64rr, X86::BSF64rm, 0 },
>>>> + { X86::BSR16rr, X86::BSR16rm, 0 },
>>>> + { X86::BSR32rr, X86::BSR32rm, 0 },
>>>> + { X86::BSR64rr, X86::BSR64rm, 0 },
>>>> + { X86::CMP16rr, X86::CMP16rm, 0 },
>>>> + { X86::CMP32rr, X86::CMP32rm, 0 },
>>>> + { X86::CMP64rr, X86::CMP64rm, 0 },
>>>> + { X86::CMP8rr, X86::CMP8rm, 0 },
>>>> + { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
>>>> + { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
>>>> + { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
>>>> + { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
>>>> + { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
>>>> + { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
>>>> + { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
>>>> + { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
>>>> + { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
>>>> + { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
>>>> + { X86::IMUL16rri, X86::IMUL16rmi, 0 },
>>>> + { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
>>>> + { X86::IMUL32rri, X86::IMUL32rmi, 0 },
>>>> + { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
>>>> + { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
>>>> + { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
>>>> + { X86::Int_COMISDrr, X86::Int_COMISDrm, TB_NO_REVERSE },
>>>> + { X86::Int_COMISSrr, X86::Int_COMISSrm, TB_NO_REVERSE },
>>>> + { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, TB_NO_REVERSE },
>>>> + { X86::CVTSD2SIrr, X86::CVTSD2SIrm, TB_NO_REVERSE },
>>>> + { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, TB_NO_REVERSE },
>>>> + { X86::CVTSS2SIrr, X86::CVTSS2SIrm, TB_NO_REVERSE },
>>>> + { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_NO_REVERSE },
>>>> + { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
>>>> + { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
>>>> + { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
>>>> + { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
>>>> + { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_NO_REVERSE },
>>>> + { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
>>>> + { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
>>>> + { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, TB_NO_REVERSE },
>>>> + { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, TB_NO_REVERSE },
>>>> + { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, TB_NO_REVERSE },
>>>> + { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, TB_NO_REVERSE },
>>>> + { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, TB_NO_REVERSE },
>>>> + { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, TB_NO_REVERSE },
>>>> + { X86::MOV16rr, X86::MOV16rm, 0 },
>>>> + { X86::MOV32rr, X86::MOV32rm, 0 },
>>>> + { X86::MOV64rr, X86::MOV64rm, 0 },
>>>> + { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
>>>> + { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
>>>> + { X86::MOV8rr, X86::MOV8rm, 0 },
>>>> + { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
>>>> + { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
>>>> + { X86::MOVDDUPrr, X86::MOVDDUPrm, TB_NO_REVERSE },
>>>> + { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
>>>> + { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
>>>> + { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
>>>> + { X86::MOVDQUrr, X86::MOVDQUrm, 0 },
>>>> + { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
>>>> + { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
>>>> + { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
>>>> + { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
>>>> + { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
>>>> + { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
>>>> + { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
>>>> + { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
>>>> + { X86::MOVUPDrr, X86::MOVUPDrm, 0 },
>>>> + { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
>>>> + { X86::MOVZPQILo2PQIrr, X86::MOVQI2PQIrm, TB_NO_REVERSE },
>>>> + { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
>>>> + { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
>>>> + { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
>>>> + { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
>>>> + { X86::PABSBrr, X86::PABSBrm, TB_ALIGN_16 },
>>>> + { X86::PABSDrr, X86::PABSDrm, TB_ALIGN_16 },
>>>> + { X86::PABSWrr, X86::PABSWrm, TB_ALIGN_16 },
>>>> + { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
>>>> + { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
>>>> + { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
>>>> + { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
>>>> + { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
>>>> + { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_NO_REVERSE },
>>>> + { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_NO_REVERSE },
>>>> + { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_NO_REVERSE },
>>>> + { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_NO_REVERSE },
>>>> + { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_NO_REVERSE },
>>>> + { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_NO_REVERSE },
>>>> + { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_NO_REVERSE },
>>>> + { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_NO_REVERSE },
>>>> + { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_NO_REVERSE },
>>>> + { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_NO_REVERSE },
>>>> + { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_NO_REVERSE },
>>>> + { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_NO_REVERSE },
>>>> + { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
>>>> + { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
>>>> + { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
>>>> + { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
>>>> + { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
>>>> + { X86::RCPSSr, X86::RCPSSm, 0 },
>>>> + { X86::RCPSSr_Int, X86::RCPSSm_Int, TB_NO_REVERSE },
>>>> + { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
>>>> + { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
>>>> + { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
>>>> + { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
>>>> + { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
>>>> + { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
>>>> + { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, TB_NO_REVERSE },
>>>> + { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
>>>> + { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
>>>> + { X86::SQRTSDr, X86::SQRTSDm, 0 },
>>>> + { X86::SQRTSDr_Int, X86::SQRTSDm_Int, TB_NO_REVERSE },
>>>> + { X86::SQRTSSr, X86::SQRTSSm, 0 },
>>>> + { X86::SQRTSSr_Int, X86::SQRTSSm_Int, TB_NO_REVERSE },
>>>> + { X86::TEST16rr, X86::TEST16rm, 0 },
>>>> + { X86::TEST32rr, X86::TEST32rm, 0 },
>>>> + { X86::TEST64rr, X86::TEST64rm, 0 },
>>>> + { X86::TEST8rr, X86::TEST8rm, 0 },
>>>> + // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
>>>> + { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
>>>> + { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
>>>> +
>>>> + // MMX version of foldable instructions
>>>> + { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
>>>> + { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
>>>> + { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
>>>> + { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
>>>> + { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
>>>> + { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
>>>> + { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
>>>> + { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
>>>> + { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
>>>> + { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
>>>> +
>>>> + // 3DNow! version of foldable instructions
>>>> + { X86::PF2IDrr, X86::PF2IDrm, 0 },
>>>> + { X86::PF2IWrr, X86::PF2IWrm, 0 },
>>>> + { X86::PFRCPrr, X86::PFRCPrm, 0 },
>>>> + { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
>>>> + { X86::PI2FDrr, X86::PI2FDrm, 0 },
>>>> + { X86::PI2FWrr, X86::PI2FWrm, 0 },
>>>> + { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
>>>> +
>>>> + // AVX 128-bit versions of foldable instructions
>>>> + { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, TB_NO_REVERSE },
>>>> + { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, TB_NO_REVERSE },
>>>> + { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, TB_NO_REVERSE },
>>>> + { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, TB_NO_REVERSE },
>>>> + { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
>>>> + { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,TB_NO_REVERSE },
>>>> + { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
>>>> + { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, TB_NO_REVERSE },
>>>> + { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
>>>> + { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,TB_NO_REVERSE },
>>>> + { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
>>>> + { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, TB_NO_REVERSE },
>>>> + { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, TB_NO_REVERSE },
>>>> + { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, TB_NO_REVERSE },
>>>> + { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, TB_NO_REVERSE },
>>>> + { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, TB_NO_REVERSE },
>>>> + { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, TB_NO_REVERSE },
>>>> + { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
>>>> + { X86::VCVTPD2DQrr, X86::VCVTPD2DQrm, 0 },
>>>> + { X86::VCVTPD2PSrr, X86::VCVTPD2PSrm, 0 },
>>>> + { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
>>>> + { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, TB_NO_REVERSE },
>>>> + { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQrm, 0 },
>>>> + { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
>>>> + { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
>>>> + { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
>>>> + { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
>>>> + { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
>>>> + { X86::VMOVDDUPrr, X86::VMOVDDUPrm, TB_NO_REVERSE },
>>>> + { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
>>>> + { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
>>>> + { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
>>>> + { X86::VMOVDQUrr, X86::VMOVDQUrm, 0 },
>>>> + { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
>>>> + { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
>>>> + { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
>>>> + { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
>>>> + { X86::VMOVZPQILo2PQIrr,X86::VMOVQI2PQIrm, TB_NO_REVERSE },
>>>> + { X86::VPABSBrr, X86::VPABSBrm, 0 },
>>>> + { X86::VPABSDrr, X86::VPABSDrm, 0 },
>>>> + { X86::VPABSWrr, X86::VPABSWrm, 0 },
>>>> + { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
>>>> + { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
>>>> + { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
>>>> + { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
>>>> + { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
>>>> + { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
>>>> + { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
>>>> + { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, TB_NO_REVERSE },
>>>> + { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
>>>> + { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
>>>> + { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
>>>> + { X86::VPTESTrr, X86::VPTESTrm, 0 },
>>>> + { X86::VRCPPSr, X86::VRCPPSm, 0 },
>>>> + { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
>>>> + { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
>>>> + { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
>>>> + { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
>>>> + { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
>>>> + { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
>>>> + { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
>>>> + { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
>>>> + { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
>>>> +
>>>> + // AVX 256-bit foldable instructions
>>>> + { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, TB_NO_REVERSE },
>>>> + { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
>>>> + { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
>>>> + { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
>>>> + { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
>>>> + { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, TB_NO_REVERSE },
>>>> + { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
>>>> + { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
>>>> + { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
>>>> + { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
>>>> + { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
>>>> + { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
>>>> + { X86::VMOVDQUYrr, X86::VMOVDQUYrm, 0 },
>>>> + { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
>>>> + { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
>>>> + { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
>>>> + { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
>>>> + { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
>>>> + { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
>>>> + { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
>>>> + { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
>>>> + { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
>>>> + { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
>>>> + { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
>>>> + { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
>>>> + { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
>>>> + { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
>>>> + { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
>>>> +
>>>> + // AVX2 foldable instructions
>>>> +
>>>> + // VBROADCASTS{SD}rr register instructions were an AVX2 addition
>>>> while the
>>>> + // VBROADCASTS{SD}rm memory instructions were available from AVX1.
>>>> + // TB_NO_REVERSE prevents unfolding from introducing an illegal
>>>> instruction
>>>> + // on AVX1 targets. The VPBROADCAST instructions are all AVX2
>>>> instructions
>>>> + // so they don't need an equivalent limitation.
>>>> + { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
>>>> + { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
>>>> + { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
>>>> + { X86::VPABSBYrr, X86::VPABSBYrm, 0 },
>>>> + { X86::VPABSDYrr, X86::VPABSDYrm, 0 },
>>>> + { X86::VPABSWYrr, X86::VPABSWYrm, 0 },
>>>> + { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, TB_NO_REVERSE },
>>>> + { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, TB_NO_REVERSE },
>>>> + { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, TB_NO_REVERSE },
>>>> + { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, TB_NO_REVERSE },
>>>> + { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, TB_NO_REVERSE },
>>>> + { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, TB_NO_REVERSE },
>>>> + { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, TB_NO_REVERSE },
>>>> + { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, TB_NO_REVERSE },
>>>> + { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
>>>> + { X86::VPERMQYri, X86::VPERMQYmi, 0 },
>>>> + { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
>>>> + { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
>>>> + { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
>>>> + { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
>>>> + { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
>>>> + { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
>>>> + { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, TB_NO_REVERSE },
>>>> + { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
>>>> + { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
>>>> + { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
>>>> +
>>>> + // XOP foldable instructions
>>>> + { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
>>>> + { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
>>>> + { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
>>>> + { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
>>>> + { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
>>>> + { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
>>>> + { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
>>>> + { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
>>>> + { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
>>>> + { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
>>>> + { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
>>>> + { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
>>>> + { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
>>>> + { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
>>>> + { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
>>>> + { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
>>>> + { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
>>>> + { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
>>>> + { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
>>>> + { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
>>>> + { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
>>>> + { X86::VPROTBri, X86::VPROTBmi, 0 },
>>>> + { X86::VPROTBrr, X86::VPROTBmr, 0 },
>>>> + { X86::VPROTDri, X86::VPROTDmi, 0 },
>>>> + { X86::VPROTDrr, X86::VPROTDmr, 0 },
>>>> + { X86::VPROTQri, X86::VPROTQmi, 0 },
>>>> + { X86::VPROTQrr, X86::VPROTQmr, 0 },
>>>> + { X86::VPROTWri, X86::VPROTWmi, 0 },
>>>> + { X86::VPROTWrr, X86::VPROTWmr, 0 },
>>>> + { X86::VPSHABrr, X86::VPSHABmr, 0 },
>>>> + { X86::VPSHADrr, X86::VPSHADmr, 0 },
>>>> + { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
>>>> + { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
>>>> + { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
>>>> + { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
>>>> + { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
>>>> + { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
>>>> +
>>>> + // LWP foldable instructions
>>>> + { X86::LWPINS32rri, X86::LWPINS32rmi, 0 },
>>>> + { X86::LWPINS64rri, X86::LWPINS64rmi, 0 },
>>>> + { X86::LWPVAL32rri, X86::LWPVAL32rmi, 0 },
>>>> + { X86::LWPVAL64rri, X86::LWPVAL64rmi, 0 },
>>>> +
>>>> + // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
>>>> + { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
>>>> + { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
>>>> + { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
>>>> + { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
>>>> + { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
>>>> + { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
>>>> + { X86::BLCI32rr, X86::BLCI32rm, 0 },
>>>> + { X86::BLCI64rr, X86::BLCI64rm, 0 },
>>>> + { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
>>>> + { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
>>>> + { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
>>>> + { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
>>>> + { X86::BLCS32rr, X86::BLCS32rm, 0 },
>>>> + { X86::BLCS64rr, X86::BLCS64rm, 0 },
>>>> + { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
>>>> + { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
>>>> + { X86::BLSI32rr, X86::BLSI32rm, 0 },
>>>> + { X86::BLSI64rr, X86::BLSI64rm, 0 },
>>>> + { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
>>>> + { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
>>>> + { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
>>>> + { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
>>>> + { X86::BLSR32rr, X86::BLSR32rm, 0 },
>>>> + { X86::BLSR64rr, X86::BLSR64rm, 0 },
>>>> + { X86::BZHI32rr, X86::BZHI32rm, 0 },
>>>> + { X86::BZHI64rr, X86::BZHI64rm, 0 },
>>>> + { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
>>>> + { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
>>>> + { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
>>>> + { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
>>>> + { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
>>>> + { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
>>>> + { X86::RORX32ri, X86::RORX32mi, 0 },
>>>> + { X86::RORX64ri, X86::RORX64mi, 0 },
>>>> + { X86::SARX32rr, X86::SARX32rm, 0 },
>>>> + { X86::SARX64rr, X86::SARX64rm, 0 },
>>>> + { X86::SHRX32rr, X86::SHRX32rm, 0 },
>>>> + { X86::SHRX64rr, X86::SHRX64rm, 0 },
>>>> + { X86::SHLX32rr, X86::SHLX32rm, 0 },
>>>> + { X86::SHLX64rr, X86::SHLX64rm, 0 },
>>>> + { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
>>>> + { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
>>>> + { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
>>>> + { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
>>>> + { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
>>>> + { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
>>>> + { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
>>>> +
>>>> + // AVX-512 foldable instructions
>>>> + { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
>>>> + { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
>>>> + { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
>>>> + { X86::VMOV64toSDZrr, X86::VMOV64toSDZrm, 0 },
>>>> + { X86::VMOVDI2PDIZrr, X86::VMOVDI2PDIZrm, 0 },
>>>> + { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
>>>> + { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
>>>> + { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
>>>> + { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
>>>> + { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
>>>> + { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
>>>> + { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
>>>> + { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
>>>> + { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
>>>> + { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
>>>> + { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
>>>> + { X86::VMOVZPQILo2PQIZrr,X86::VMOVQI2PQIZrm, TB_NO_REVERSE },
>>>> + { X86::VPABSBZrr, X86::VPABSBZrm, 0 },
>>>> + { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
>>>> + { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
>>>> + { X86::VPABSWZrr, X86::VPABSWZrm, 0 },
>>>> + { X86::VPERMILPDZri, X86::VPERMILPDZmi, 0 },
>>>> + { X86::VPERMILPSZri, X86::VPERMILPSZmi, 0 },
>>>> + { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
>>>> + { X86::VPERMQZri, X86::VPERMQZmi, 0 },
>>>> + { X86::VPMOVSXBDZrr, X86::VPMOVSXBDZrm, 0 },
>>>> + { X86::VPMOVSXBQZrr, X86::VPMOVSXBQZrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBWZrr, X86::VPMOVSXBWZrm, 0 },
>>>> + { X86::VPMOVSXDQZrr, X86::VPMOVSXDQZrm, 0 },
>>>> + { X86::VPMOVSXWDZrr, X86::VPMOVSXWDZrm, 0 },
>>>> + { X86::VPMOVSXWQZrr, X86::VPMOVSXWQZrm, 0 },
>>>> + { X86::VPMOVZXBDZrr, X86::VPMOVZXBDZrm, 0 },
>>>> + { X86::VPMOVZXBQZrr, X86::VPMOVZXBQZrm, TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBWZrr, X86::VPMOVZXBWZrm, 0 },
>>>> + { X86::VPMOVZXDQZrr, X86::VPMOVZXDQZrm, 0 },
>>>> + { X86::VPMOVZXWDZrr, X86::VPMOVZXWDZrm, 0 },
>>>> + { X86::VPMOVZXWQZrr, X86::VPMOVZXWQZrm, 0 },
>>>> + { X86::VPOPCNTDZrr, X86::VPOPCNTDZrm, 0 },
>>>> + { X86::VPOPCNTQZrr, X86::VPOPCNTQZrm, 0 },
>>>> + { X86::VPSHUFDZri, X86::VPSHUFDZmi, 0 },
>>>> + { X86::VPSHUFHWZri, X86::VPSHUFHWZmi, 0 },
>>>> + { X86::VPSHUFLWZri, X86::VPSHUFLWZmi, 0 },
>>>> + { X86::VPSLLDQZ512rr, X86::VPSLLDQZ512rm, 0 },
>>>> + { X86::VPSLLDZri, X86::VPSLLDZmi, 0 },
>>>> + { X86::VPSLLQZri, X86::VPSLLQZmi, 0 },
>>>> + { X86::VPSLLWZri, X86::VPSLLWZmi, 0 },
>>>> + { X86::VPSRADZri, X86::VPSRADZmi, 0 },
>>>> + { X86::VPSRAQZri, X86::VPSRAQZmi, 0 },
>>>> + { X86::VPSRAWZri, X86::VPSRAWZmi, 0 },
>>>> + { X86::VPSRLDQZ512rr, X86::VPSRLDQZ512rm, 0 },
>>>> + { X86::VPSRLDZri, X86::VPSRLDZmi, 0 },
>>>> + { X86::VPSRLQZri, X86::VPSRLQZmi, 0 },
>>>> + { X86::VPSRLWZri, X86::VPSRLWZmi, 0 },
>>>> +
>>>> + // AVX-512 foldable instructions (256-bit versions)
>>>> + { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m,
>>>> TB_NO_REVERSE },
>>>> + { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m,
>>>> TB_NO_REVERSE },
>>>> + { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm,
>>>> TB_ALIGN_32 },
>>>> + { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm,
>>>> TB_ALIGN_32 },
>>>> + { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm,
>>>> TB_ALIGN_32 },
>>>> + { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm,
>>>> TB_ALIGN_32 },
>>>> + { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
>>>> + { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
>>>> + { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
>>>> + { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
>>>> + { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
>>>> + { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
>>>> + { X86::VPABSBZ256rr, X86::VPABSBZ256rm, 0 },
>>>> + { X86::VPABSDZ256rr, X86::VPABSDZ256rm, 0 },
>>>> + { X86::VPABSQZ256rr, X86::VPABSQZ256rm, 0 },
>>>> + { X86::VPABSWZ256rr, X86::VPABSWZ256rm, 0 },
>>>> + { X86::VPERMILPDZ256ri, X86::VPERMILPDZ256mi, 0 },
>>>> + { X86::VPERMILPSZ256ri, X86::VPERMILPSZ256mi, 0 },
>>>> + { X86::VPERMPDZ256ri, X86::VPERMPDZ256mi, 0 },
>>>> + { X86::VPERMQZ256ri, X86::VPERMQZ256mi, 0 },
>>>> + { X86::VPMOVSXBDZ256rr, X86::VPMOVSXBDZ256rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBQZ256rr, X86::VPMOVSXBQZ256rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBWZ256rr, X86::VPMOVSXBWZ256rm, 0 },
>>>> + { X86::VPMOVSXDQZ256rr, X86::VPMOVSXDQZ256rm, 0 },
>>>> + { X86::VPMOVSXWDZ256rr, X86::VPMOVSXWDZ256rm, 0 },
>>>> + { X86::VPMOVSXWQZ256rr, X86::VPMOVSXWQZ256rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBDZ256rr, X86::VPMOVZXBDZ256rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBQZ256rr, X86::VPMOVZXBQZ256rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBWZ256rr, X86::VPMOVZXBWZ256rm, 0 },
>>>> + { X86::VPMOVZXDQZ256rr, X86::VPMOVZXDQZ256rm, 0 },
>>>> + { X86::VPMOVZXWDZ256rr, X86::VPMOVZXWDZ256rm, 0 },
>>>> + { X86::VPMOVZXWQZ256rr, X86::VPMOVZXWQZ256rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPSHUFDZ256ri, X86::VPSHUFDZ256mi, 0 },
>>>> + { X86::VPSHUFHWZ256ri, X86::VPSHUFHWZ256mi, 0 },
>>>> + { X86::VPSHUFLWZ256ri, X86::VPSHUFLWZ256mi, 0 },
>>>> + { X86::VPSLLDQZ256rr, X86::VPSLLDQZ256rm, 0 },
>>>> + { X86::VPSLLDZ256ri, X86::VPSLLDZ256mi, 0 },
>>>> + { X86::VPSLLQZ256ri, X86::VPSLLQZ256mi, 0 },
>>>> + { X86::VPSLLWZ256ri, X86::VPSLLWZ256mi, 0 },
>>>> + { X86::VPSRADZ256ri, X86::VPSRADZ256mi, 0 },
>>>> + { X86::VPSRAQZ256ri, X86::VPSRAQZ256mi, 0 },
>>>> + { X86::VPSRAWZ256ri, X86::VPSRAWZ256mi, 0 },
>>>> + { X86::VPSRLDQZ256rr, X86::VPSRLDQZ256rm, 0 },
>>>> + { X86::VPSRLDZ256ri, X86::VPSRLDZ256mi, 0 },
>>>> + { X86::VPSRLQZ256ri, X86::VPSRLQZ256mi, 0 },
>>>> + { X86::VPSRLWZ256ri, X86::VPSRLWZ256mi, 0 },
>>>> +
>>>> + // AVX-512 foldable instructions (128-bit versions)
>>>> + { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m,
>>>> TB_NO_REVERSE },
>>>> + { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm,
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm,
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm,
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm,
>>>> TB_ALIGN_16 },
>>>> + { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
>>>> + { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
>>>> + { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
>>>> + { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
>>>> + { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
>>>> + { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
>>>> + { X86::VPABSBZ128rr, X86::VPABSBZ128rm, 0 },
>>>> + { X86::VPABSDZ128rr, X86::VPABSDZ128rm, 0 },
>>>> + { X86::VPABSQZ128rr, X86::VPABSQZ128rm, 0 },
>>>> + { X86::VPABSWZ128rr, X86::VPABSWZ128rm, 0 },
>>>> + { X86::VPERMILPDZ128ri, X86::VPERMILPDZ128mi, 0 },
>>>> + { X86::VPERMILPSZ128ri, X86::VPERMILPSZ128mi, 0 },
>>>> + { X86::VPMOVSXBDZ128rr, X86::VPMOVSXBDZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBQZ128rr, X86::VPMOVSXBQZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVSXBWZ128rr, X86::VPMOVSXBWZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVSXDQZ128rr, X86::VPMOVSXDQZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVSXWDZ128rr, X86::VPMOVSXWDZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVSXWQZ128rr, X86::VPMOVSXWQZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBDZ128rr, X86::VPMOVZXBDZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBQZ128rr, X86::VPMOVZXBQZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXBWZ128rr, X86::VPMOVZXBWZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXDQZ128rr, X86::VPMOVZXDQZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXWDZ128rr, X86::VPMOVZXWDZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPMOVZXWQZ128rr, X86::VPMOVZXWQZ128rm,
>>>> TB_NO_REVERSE },
>>>> + { X86::VPSHUFDZ128ri, X86::VPSHUFDZ128mi, 0 },
>>>> + { X86::VPSHUFHWZ128ri, X86::VPSHUFHWZ128mi, 0 },
>>>> + { X86::VPSHUFLWZ128ri, X86::VPSHUFLWZ128mi, 0 },
>>>> + { X86::VPSLLDQZ128rr, X86::VPSLLDQZ128rm, 0 },
>>>> + { X86::VPSLLDZ128ri, X86::VPSLLDZ128mi, 0 },
>>>> + { X86::VPSLLQZ128ri, X86::VPSLLQZ128mi, 0 },
>>>> + { X86::VPSLLWZ128ri, X86::VPSLLWZ128mi, 0 },
>>>> + { X86::VPSRADZ128ri, X86::VPSRADZ128mi, 0 },
>>>> + { X86::VPSRAQZ128ri, X86::VPSRAQZ128mi, 0 },
>>>> + { X86::VPSRAWZ128ri, X86::VPSRAWZ128mi, 0 },
>>>> + { X86::VPSRLDQZ128rr, X86::VPSRLDQZ128rm, 0 },
>>>> + { X86::VPSRLDZ128ri, X86::VPSRLDZ128mi, 0 },
>>>> + { X86::VPSRLQZ128ri, X86::VPSRLQZ128mi, 0 },
>>>> + { X86::VPSRLWZ128ri, X86::VPSRLWZ128mi, 0 },
>>>> +
>>>> + // F16C foldable instructions
>>>> + { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
>>>> + { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
>>>> +
>>>> + // AES foldable instructions
>>>> + { X86::AESIMCrr, X86::AESIMCrm,
>>>> TB_ALIGN_16 },
>>>> + { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm,
>>>> TB_ALIGN_16 },
>>>> + { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
>>>> + { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
>>>> + };
>>>> +
>>>> for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
>>>> AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
>>>> Entry.RegOp, Entry.MemOp,
>>>> @@ -143,6 +1042,1396 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
>>>> Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
>>>> }
>>>>
>>>> + static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
>>>> + { X86::ADC32rr, X86::ADC32rm, 0 },
>>>> + { X86::ADC64rr, X86::ADC64rm, 0 },
>>>> + { X86::ADD16rr, X86::ADD16rm, 0 },
>>>> + { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
>>>>
>>> + { X86::ADD32rr, X86::ADD32rm, 0 },
>>>> + { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
>>>> + { X86::ADD64rr, X86::ADD64rm, 0 },
>>>> + { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
>>>> + { X86::ADD8rr, X86::ADD8rm, 0 },
>>>> + { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
>>>> + { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
>>>> + { X86::ADDSDrr, X86::ADDSDrm, 0 },
>>>> + { X86::ADDSDrr_Int, X86::ADDSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::ADDSSrr, X86::ADDSSrm, 0 },
>>>> + { X86::ADDSSrr_Int, X86::ADDSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
>>>> + { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
>>>> + { X86::AND16rr, X86::AND16rm, 0 },
>>>> + { X86::AND32rr, X86::AND32rm, 0 },
>>>> + { X86::AND64rr, X86::AND64rm, 0 },
>>>> + { X86::AND8rr, X86::AND8rm, 0 },
>>>> + { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
>>>> + { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
>>>> + { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
>>>> + { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
>>>> + { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
>>>> + { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
>>>> + { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
>>>> + { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
>>>> + { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
>>>> + { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
>>>> + { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
>>>> + { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
>>>> + { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
>>>> + { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
>>>> + { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
>>>> + { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
>>>> + { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
>>>> + { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
>>>> + { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
>>>> + { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
>>>> + { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
>>>> + { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
>>>> + { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
>>>> + { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
>>>> + { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
>>>> + { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
>>>> + { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
>>>> + { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
>>>> + { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
>>>> + { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
>>>> + { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
>>>> + { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
>>>> + { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
>>>> + { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
>>>> + { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
>>>> + { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
>>>> + { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
>>>> + { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
>>>> + { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
>>>> + { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
>>>> + { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
>>>> + { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
>>>> + { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
>>>> + { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
>>>> + { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
>>>> + { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
>>>> + { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
>>>> + { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
>>>> + { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
>>>> + { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
>>>> + { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
>>>> + { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
>>>> + { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
>>>> + { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
>>>> + { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
>>>> + { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
>>>> + { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
>>>> + { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
>>>> + { X86::CMPSDrr, X86::CMPSDrm, 0 },
>>>> + { X86::CMPSSrr, X86::CMPSSrm, 0 },
>>>> + { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
>>>> + { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
>>>> + { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
>>>> + { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
>>>> + { X86::DIVSDrr, X86::DIVSDrm, 0 },
>>>> + { X86::DIVSDrr_Int, X86::DIVSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::DIVSSrr, X86::DIVSSrm, 0 },
>>>> + { X86::DIVSSrr_Int, X86::DIVSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
>>>> + { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
>>>> + { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
>>>> + { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
>>>> + { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
>>>> + { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
>>>> + { X86::IMUL16rr, X86::IMUL16rm, 0 },
>>>> + { X86::IMUL32rr, X86::IMUL32rm, 0 },
>>>> + { X86::IMUL64rr, X86::IMUL64rm, 0 },
>>>> + { X86::Int_CMPSDrr, X86::Int_CMPSDrm, TB_NO_REVERSE },
>>>> + { X86::Int_CMPSSrr, X86::Int_CMPSSrm, TB_NO_REVERSE },
>>>> + { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, TB_NO_REVERSE },
>>>> + { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
>>>> + { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
>>>> + { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
>>>> + { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
>>>> + { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, TB_NO_REVERSE },
>>>> + { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
>>>> + { X86::MAXCPDrr, X86::MAXCPDrm, TB_ALIGN_16 },
>>>> + { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
>>>> + { X86::MAXCPSrr, X86::MAXCPSrm, TB_ALIGN_16 },
>>>> + { X86::MAXSDrr, X86::MAXSDrm, 0 },
>>>> + { X86::MAXCSDrr, X86::MAXCSDrm, 0 },
>>>> + { X86::MAXSDrr_Int, X86::MAXSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::MAXSSrr, X86::MAXSSrm, 0 },
>>>> + { X86::MAXCSSrr, X86::MAXCSSrm, 0 },
>>>> + { X86::MAXSSrr_Int, X86::MAXSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
>>>> + { X86::MINCPDrr, X86::MINCPDrm, TB_ALIGN_16 },
>>>> + { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
>>>> + { X86::MINCPSrr, X86::MINCPSrm, TB_ALIGN_16 },
>>>> + { X86::MINSDrr, X86::MINSDrm, 0 },
>>>> + { X86::MINCSDrr, X86::MINCSDrm, 0 },
>>>> + { X86::MINSDrr_Int, X86::MINSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::MINSSrr, X86::MINSSrm, 0 },
>>>> + { X86::MINCSSrr, X86::MINCSSrm, 0 },
>>>> + { X86::MINSSrr_Int, X86::MINSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
>>>> + { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
>>>> + { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
>>>> + { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
>>>> + { X86::MULSDrr, X86::MULSDrm, 0 },
>>>> + { X86::MULSDrr_Int, X86::MULSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::MULSSrr, X86::MULSSrm, 0 },
>>>> + { X86::MULSSrr_Int, X86::MULSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::OR16rr, X86::OR16rm, 0 },
>>>> + { X86::OR32rr, X86::OR32rm, 0 },
>>>> + { X86::OR64rr, X86::OR64rm, 0 },
>>>> + { X86::OR8rr, X86::OR8rm, 0 },
>>>> + { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
>>>> + { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
>>>> + { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
>>>> + { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
>>>> + { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
>>>> + { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
>>>> + { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
>>>> + { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
>>>> + { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
>>>> + { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
>>>> + { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
>>>> + { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
>>>> + { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
>>>> + { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
>>>> + { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
>>>> + { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
>>>> + { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
>>>> + { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
>>>> + { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
>>>> + { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
>>>> + { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
>>>> + { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
>>>> + { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
>>>> + { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
>>>> + { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
>>>> + { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
>>>> + { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
>>>> + { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
>>>> + { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
>>>> + { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
>>>> + { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
>>>> + { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
>>>> + { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
>>>> + { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
>>>> + { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
>>>> + { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
>>>> + { X86::PINSRBrr, X86::PINSRBrm, 0 },
>>>> + { X86::PINSRDrr, X86::PINSRDrm, 0 },
>>>> + { X86::PINSRQrr, X86::PINSRQrm, 0 },
>>>> + { X86::PINSRWrri, X86::PINSRWrmi, 0 },
>>>> + { X86::PMADDUBSWrr, X86::PMADDUBSWrm, TB_ALIGN_16 },
>>>> + { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
>>>> + { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
>>>> + { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
>>>> + { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
>>>> + { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
>>>> + { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
>>>> + { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
>>>> + { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
>>>> + { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
>>>> + { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
>>>> + { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
>>>> + { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
>>>> + { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
>>>> + { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
>>>> + { X86::PMULHRSWrr, X86::PMULHRSWrm, TB_ALIGN_16 },
>>>> + { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
>>>> + { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
>>>> + { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
>>>> + { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
>>>> + { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
>>>> + { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
>>>> + { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
>>>> + { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
>>>> + { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
>>>> + { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
>>>> + { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
>>>> + { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
>>>> + { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
>>>> + { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
>>>> + { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
>>>> + { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
>>>> + { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
>>>> + { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
>>>> + { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
>>>> + { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
>>>> + { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
>>>> + { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
>>>> + { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
>>>> + { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
>>>> + { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
>>>> + { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
>>>> + { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
>>>> + { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
>>>> + { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
>>>> + { X86::ROUNDSDr_Int, X86::ROUNDSDm_Int, TB_NO_REVERSE },
>>>> + { X86::ROUNDSSr_Int, X86::ROUNDSSm_Int, TB_NO_REVERSE },
>>>> + { X86::SBB32rr, X86::SBB32rm, 0 },
>>>> + { X86::SBB64rr, X86::SBB64rm, 0 },
>>>> + { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
>>>> + { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
>>>> + { X86::SUB16rr, X86::SUB16rm, 0 },
>>>> + { X86::SUB32rr, X86::SUB32rm, 0 },
>>>> + { X86::SUB64rr, X86::SUB64rm, 0 },
>>>> + { X86::SUB8rr, X86::SUB8rm, 0 },
>>>> + { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
>>>> + { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
>>>> + { X86::SUBSDrr, X86::SUBSDrm, 0 },
>>>> + { X86::SUBSDrr_Int, X86::SUBSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::SUBSSrr, X86::SUBSSrm, 0 },
>>>> + { X86::SUBSSrr_Int, X86::SUBSSrm_Int, TB_NO_REVERSE },
>>>> + // FIXME: TEST*rr -> swapped operand of TEST*mr.
>>>> + { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
>>>> + { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
>>>> + { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
>>>> + { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
>>>> + { X86::XOR16rr, X86::XOR16rm, 0 },
>>>> + { X86::XOR32rr, X86::XOR32rm, 0 },
>>>> + { X86::XOR64rr, X86::XOR64rm, 0 },
>>>> + { X86::XOR8rr, X86::XOR8rm, 0 },
>>>> + { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
>>>> + { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
>>>
>>>
>>>> +
>>>> + // MMX version of foldable instructions
>>>>
>>> + { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
>>>> + { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
>>>> + { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
>>>> + { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
>>>> + { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
>>>> + { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
>>>> + { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
>>>> + { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
>>>> + { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
>>>> + { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
>>>> + { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
>>>> + { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
>>>> + { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
>>>> + { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
>>>> + { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
>>>> + { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
>>>> + { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
>>>> + { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
>>>> + { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
>>>> + { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
>>>> + { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
>>>> + { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
>>>> + { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
>>>> + { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
>>>> + { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
>>>> + { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
>>>> + { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
>>>> + { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
>>>> + { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
>>>> + { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
>>>> + { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
>>>> + { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
>>>> + { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
>>>> + { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
>>>> + { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
>>>> + { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
>>>> + { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
>>>> + { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
>>>> + { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
>>>> + { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
>>>> + { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
>>>> + { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
>>>> + { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
>>>> + { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
>>>> + { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
>>>> + { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
>>>> + { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
>>>> + { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
>>>> + { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
>>>> + { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
>>>> + { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
>>>> + { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
>>>> + { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
>>>> + { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
>>>> + { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
>>>> + { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
>>>> + { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
>>>> + { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
>>>> + { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
>>>> + { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
>>>> + { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
>>>> + { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
>>>> + { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
>>>> + { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
>>>> + { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
>>>> + { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
>>>> + { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
>>>> + { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
>>>> + { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
>>>> + { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
>>>
>>>
>>>> +
>>>> + // 3DNow! version of foldable instructions
>>>>
>>> + { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
>>>> + { X86::PFACCrr, X86::PFACCrm, 0 },
>>>> + { X86::PFADDrr, X86::PFADDrm, 0 },
>>>> + { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
>>>> + { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
>>>> + { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
>>>> + { X86::PFMAXrr, X86::PFMAXrm, 0 },
>>>> + { X86::PFMINrr, X86::PFMINrm, 0 },
>>>> + { X86::PFMULrr, X86::PFMULrm, 0 },
>>>> + { X86::PFNACCrr, X86::PFNACCrm, 0 },
>>>> + { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
>>>> + { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
>>>> + { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
>>>> + { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
>>>> + { X86::PFSUBrr, X86::PFSUBrm, 0 },
>>>> + { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
>>>> + { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
>>>
>>>
>>>> +
>>>> + // AVX 128-bit versions of foldable instructions
>>>>
>>> + { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
>>>> + { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
>>>> + { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
>>>> + { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
>>>> + { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
>>>> + { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
>>>> + { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
>>>> + { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
>>>> + { X86::VADDPDrr, X86::VADDPDrm, 0 },
>>>> + { X86::VADDPSrr, X86::VADDPSrm, 0 },
>>>> + { X86::VADDSDrr, X86::VADDSDrm, 0 },
>>>> + { X86::VADDSDrr_Int, X86::VADDSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::VADDSSrr, X86::VADDSSrm, 0 },
>>>> + { X86::VADDSSrr_Int, X86::VADDSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
>>>> + { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
>>>> + { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
>>>> + { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
>>>> + { X86::VANDPDrr, X86::VANDPDrm, 0 },
>>>> + { X86::VANDPSrr, X86::VANDPSrm, 0 },
>>>> + { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
>>>> + { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
>>>> + { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
>>>> + { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
>>>> + { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
>>>> + { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
>>>> + { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
>>>> + { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
>>>> + { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
>>>> + { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
>>>> + { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
>>>> + { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
>>>> + { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::VDPPDrri, X86::VDPPDrmi, 0 },
>>>> + { X86::VDPPSrri, X86::VDPPSrmi, 0 },
>>>> + { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
>>>> + { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
>>>> + { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
>>>> + { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
>>>> + { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, TB_NO_REVERSE },
>>>> + { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, TB_NO_REVERSE },
>>>> + { X86::VMAXCPDrr, X86::VMAXCPDrm, 0 },
>>>> + { X86::VMAXCPSrr, X86::VMAXCPSrm, 0 },
>>>> + { X86::VMAXCSDrr, X86::VMAXCSDrm, 0 },
>>>> + { X86::VMAXCSSrr, X86::VMAXCSSrm, 0 },
>>>> + { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
>>>> + { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
>>>> + { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
>>>> + { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
>>>> + { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::VMINCPDrr, X86::VMINCPDrm, 0 },
>>>> + { X86::VMINCPSrr, X86::VMINCPSrm, 0 },
>>>> + { X86::VMINCSDrr, X86::VMINCSDrm, 0 },
>>>> + { X86::VMINCSSrr, X86::VMINCSSrm, 0 },
>>>> + { X86::VMINPDrr, X86::VMINPDrm, 0 },
>>>> + { X86::VMINPSrr, X86::VMINPSrm, 0 },
>>>> + { X86::VMINSDrr, X86::VMINSDrm, 0 },
>>>> + { X86::VMINSDrr_Int, X86::VMINSDrm_Int, TB_NO_REVERSE },
>>>> + { X86::VMINSSrr, X86::VMINSSrm, 0 },
>>>> + { X86::VMINSSrr_Int, X86::VMINSSrm_Int, TB_NO_REVERSE },
>>>> + { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
>>>> + { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
>>>> + { X86::VMULPDrr, X86::VMULPDrm, 0 },
>>>> + { X86::VMULPSrr, X86::VMULPSrm, 0 },
>>>> + { X86::VMULSDrr, X86::VMULSDrm, 0 },
>>>> + { X86::VMULSDrr_Int, X86::VMULSDrm_Int, TB_NO_REVERSE },
>>>> +
>>>
>>>
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