[PATCH] D33583: [AMDGPU] Allow SDWA in instructions with immediates and SGPRs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec marked 2 inline comments as done.
rampitec added inline comments.


================
Comment at: lib/Target/AMDGPU/SIPeepholeSDWA.cpp:596-597
+        (Operand.isReg() && !TRI->isVGPR(*MRI, Operand.getReg()))) {
+      if (Desc.OpInfo[I].RegClass == -1 ||
+         !TRI->hasVGPRs(TRI->getRegClass(Desc.OpInfo[I].RegClass)))
+        return false;
----------------
rampitec wrote:
> SamWot wrote:
> > Why this check is needed? It seems redundant for me.
> Is there any guarantee that all operands can be VGPRs?
I have checked the list of supported instructions. I believe all of them accept VGPRs. I will remove the check shortly.


================
Comment at: lib/Target/AMDGPU/SIPeepholeSDWA.cpp:731
+    else if (Op.isReg())
+      Copy.addReg(Op.getReg(), Op.isKill() ? RegState::Kill : 0);
+    Op.ChangeToRegister(VGPR, false);
----------------
SamWot wrote:
> You should check for subregs
Thanks, nice catch.


Repository:
  rL LLVM

https://reviews.llvm.org/D33583