[PATCH] D33578: [DAGCombiner] use narrow load to avoid vector extract

Sanjay Patel via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu May 25 16:38:38 PDT 2017


spatel created this revision.
Herald added subscribers: javed.absar, mcrosier.

If we have (extract_subvector(load wide vector)) with no other users, that can just be (load narrow vector).

I need help to confirm that all of the test diffs are correct. When I saw how many AArch tests were changing I thought something went wrong, but on closer inspection, we just delete the '2' from all of those instructions. Hooray for mnemonics that actually make sense!

The memop chain updating is based on code that already exists multiple times in x86, so I think that should be pulled into a helper function as a follow-up. I wouldn't have gotten that sequence on my own.

Background: this is a potential improvement noticed via regressions caused by making x86's peekThroughBitcasts() not loop on consecutive bitcasts (see comments in https://reviews.llvm.org/D33137).


https://reviews.llvm.org/D33578

Files:
  lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  test/CodeGen/AArch64/arm64-vabs.ll
  test/CodeGen/AArch64/arm64-vadd.ll
  test/CodeGen/AArch64/arm64-vmul.ll
  test/CodeGen/AArch64/arm64-vshift.ll
  test/CodeGen/AArch64/arm64-vsub.ll
  test/CodeGen/ARM/vcombine.ll
  test/CodeGen/ARM/vext.ll
  test/CodeGen/X86/avx512bw-intrinsics.ll
  test/CodeGen/X86/vector-shuffle-512-v16.ll
  test/CodeGen/X86/vector-shuffle-avx512.ll
  test/CodeGen/X86/widened-broadcast.ll
  test/CodeGen/X86/x86-interleaved-access.ll

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