[PATCH] D33408: MachineCSE: Respect interblock physreg liveness
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed May 24 10:21:59 PDT 2017
Moved it in r303778.
-Krzysztof
On 5/24/2017 12:13 PM, Krzysztof Parzyszek via llvm-commits wrote:
> This test shouldn't be in that directory. test/CodeGen/MIR/ is meant for
> tests related to the MIR infrastructure itself. There are some tests in
> there that don't follow this, but new .mir files that test actual
> codegen should go into test/CodeGen/<target>.
>
> -Krzysztof
>
> On 5/24/2017 12:09 PM, Mattias Eriksson V via llvm-commits wrote:
>> Hi!
>>
>> This is my mistake. I apologize!
>>
>> I think this is the right way to fix this:
>> diff --git a/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>> b/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>> index 5206e89cf77..3866ef983ce 100644
>> --- a/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>> +++ b/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>> @@ -1,4 +1,5 @@
>> # RUN: llc -mtriple thumbv5e -run-pass=machine-cse -o - %s |
>> FileCheck %s
>> +# REQUIRES: arm
>> # This is a contrived example made to expose a bug in
>> # MachineCSE, see PR32538.
>>
>> Can someone commit this for me (or revert)? I don't have commit access
>> yet.
>>
>> --
>> Mattias
>>
>> On 05/24/17 18:27, Zachary Turner wrote:
>>> Hello, this new test fails for me.
>>>
>>> FAIL: LLVM :: CodeGen/MIR/Generic/machine-cse-physreg.mir (6862 of
>>> 20759)
>>> ******************** TEST 'LLVM ::
>>> CodeGen/MIR/Generic/machine-cse-physreg.mir' FAILED ********************
>>> Script:
>>> --
>>> D:/src/llvmbuild/ninja/./bin\llc.EXE -mtriple thumbv5e
>>> -run-pass=machine-cse -o -
>>> D:\src\llvm-mono\llvm\test\CodeGen\MIR\Generic\machine-cse-physreg.mir |
>>> D:/src/llvmbuild/ninja/./bin\FileCheck.EXE
>>> D:\src\llvm-mono\llvm\test\CodeGen\MIR\Generic\machine-cse-physreg.mir
>>> --
>>> Exit Code: 2
>>>
>>> Command Output (stdout):
>>> --
>>> $ "D:/src/llvmbuild/ninja/./bin\llc.EXE" "-mtriple" "thumbv5e"
>>> "-run-pass=machine-cse" "-o" "-"
>>> "D:\src\llvm-mono\llvm\test\CodeGen\MIR\Generic\machine-cse-physreg.mir"
>>> # command stderr:
>>> D:/src/llvmbuild/ninja/./bin\llc.EXE: : error: unable to get target for
>>> 'thumbv5e', see --version and --triple.
>>>
>>> error: command failed with exit status: 1
>>> $ "D:/src/llvmbuild/ninja/./bin\FileCheck.EXE"
>>> "D:\src\llvm-mono\llvm\test\CodeGen\MIR\Generic\machine-cse-physreg.mir"
>>> # command stderr:
>>> FileCheck error: '-' is empty.
>>> FileCheck command line: D:/src/llvmbuild/ninja/./bin\FileCheck.EXE
>>> D:\src\llvm-mono\llvm\test\CodeGen\MIR\Generic\machine-cse-physreg.mir
>>>
>>> error: command failed with exit status: 2
>>>
>>> --
>>>
>>> I compile with LLVM_TARGETS_TO_BUILD=X86. It looks like perhaps this
>>> test assumes that thumb target is available? Can you please fix the
>>> test to not fail when the appropriate target is not available?
>>>
>>> On Wed, May 24, 2017 at 2:35 AM Mikael Holmén via Phabricator via
>>> llvm-commits <llvm-commits at lists.llvm.org
>>> <mailto:llvm-commits at lists.llvm.org>> wrote:
>>>
>>> This revision was automatically updated to reflect the committed
>>> changes.
>>> Closed by commit rL303731: MachineCSE: Respect interblock physreg
>>> liveness (authored by uabelho).
>>>
>>> Changed prior to commit:
>>> https://reviews.llvm.org/D33408?vs=99746&id=100057#toc
>>>
>>> Repository:
>>> rL LLVM
>>>
>>> https://reviews.llvm.org/D33408
>>>
>>> Files:
>>> llvm/trunk/lib/CodeGen/MachineCSE.cpp
>>> llvm/trunk/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>>>
>>>
>>> Index: llvm/trunk/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>>> ===================================================================
>>> --- llvm/trunk/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>>> +++ llvm/trunk/test/CodeGen/MIR/Generic/machine-cse-physreg.mir
>>> @@ -0,0 +1,35 @@
>>> +# RUN: llc -mtriple thumbv5e -run-pass=machine-cse -o - %s |
>>> FileCheck %s
>>> +
>>> +# This is a contrived example made to expose a bug in
>>> +# MachineCSE, see PR32538.
>>> +
>>> +# MachineCSE must not remove this def of %cpsr:
>>> +# CHECK-LABEL: bb.1:
>>> +# CHECK: , %cpsr = tLSLri
>>> +
>>> +...
>>> +---
>>> +name: spam
>>> +registers:
>>> + - { id: 0, class: tgpr }
>>> + - { id: 1, class: tgpr }
>>> + - { id: 2, class: tgpr }
>>> + - { id: 3, class: tgpr }
>>> +liveins:
>>> + - { reg: '%r0', virtual-reg: '%0' }
>>> +body: |
>>> + bb.0:
>>> + liveins: %r0
>>> + %0 = COPY %r0
>>> + %1, %cpsr = tLSLri %0, 2, 14, _
>>> + tCMPi8 %0, 5, 14, _, implicit-def %cpsr
>>> + tBcc %bb.8, 8, %cpsr
>>> +
>>> + bb.1:
>>> + %2, %cpsr = tLSLri %0, 2, 14, _
>>> +
>>> + bb.8:
>>> + liveins: %cpsr
>>> + %3 = COPY %cpsr
>>> + tSTRi killed %3, %0, 0, 14, _
>>> +...
>>> Index: llvm/trunk/lib/CodeGen/MachineCSE.cpp
>>> ===================================================================
>>> --- llvm/trunk/lib/CodeGen/MachineCSE.cpp
>>> +++ llvm/trunk/lib/CodeGen/MachineCSE.cpp
>>> @@ -180,8 +180,8 @@
>>> I = skipDebugInstructionsForward(I, E);
>>>
>>> if (I == E)
>>> - // Reached end of block, register is obviously dead.
>>> - return true;
>>> + // Reached end of block, we don't know if register is
>>> dead or
>>> not.
>>> + return false;
>>>
>>> bool SeenDef = false;
>>> for (const MachineOperand &MO : I->operands()) {
>>>
>>>
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