[PATCH] D33408: MachineCSE: Respect interblock physreg liveness

[mattias.v.eriksson@ericsson.com via Phabricator via llvm-commits]

materi created this revision.

This is a fix for PR32538. MachineCSE first looks at MO.isDead(), but
if it is not marked dead, MachineCSE still wants to do its own check
to see if it is trivially dead. This check for the trivial case
assumed that physical registers cannot be live out of a block.


https://reviews.llvm.org/D33408

Files:
  lib/CodeGen/MachineCSE.cpp
  test/CodeGen/MIR/Generic/machine-cse-physreg.mir


Index: test/CodeGen/MIR/Generic/machine-cse-physreg.mir
===================================================================
--- /dev/null
+++ test/CodeGen/MIR/Generic/machine-cse-physreg.mir
@@ -0,0 +1,35 @@
+# RUN: llc -mtriple thumbv5e -run-pass=machine-cse -o - %s | FileCheck %s
+
+# This is a contrived example made to expose a bug in
+# MachineCSE, see PR32538.
+
+# MachineCSE must not remove this def of %cpsr:
+# CHECK-LABEL: bb.1:
+# CHECK: , %cpsr = tLSLri
+
+...
+---
+name:            spam
+registers:
+  - { id: 0, class: tgpr }
+  - { id: 1, class: tgpr }
+  - { id: 2, class: tgpr }
+  - { id: 3, class: tgpr }
+liveins:
+  - { reg: '%r0', virtual-reg: '%0' }
+body:             |
+  bb.0:
+    liveins: %r0
+    %0 = COPY %r0
+    %1, %cpsr = tLSLri %0, 2, 14, _
+    tCMPi8 %0, 5, 14, _, implicit-def %cpsr
+    tBcc %bb.8, 8, %cpsr
+
+  bb.1:
+    %2, %cpsr = tLSLri %0, 2, 14, _
+
+  bb.8:
+    liveins: %cpsr
+    %3 = COPY %cpsr
+    tSTRi killed %3, %0, 0, 14, _
+...
Index: lib/CodeGen/MachineCSE.cpp
===================================================================
--- lib/CodeGen/MachineCSE.cpp
+++ lib/CodeGen/MachineCSE.cpp
@@ -180,8 +180,8 @@
     I = skipDebugInstructionsForward(I, E);
 
     if (I == E)
-      // Reached end of block, register is obviously dead.
-      return true;
+      // Reached end of block, we don't know if register is dead or not.
+      return false;
 
     bool SeenDef = false;
     for (const MachineOperand &MO : I->operands()) {


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