[llvm] r303341 - Re-commit: [globalisel][tablegen] Import rules containing intrinsic_wo_chain.
Daniel Sanders via llvm-commits
llvm-commits at lists.llvm.org
Mon May 22 02:15:51 PDT 2017
A compile time regression is to be expected since this commit triples the number of rules that get imported from SelectionDAG but I agree that if it's causing buildbots to fail then it's much too high. It's weird that I don't get this degree of regression though. 'ninja' was a matter of seconds for me last week and I've just repeated that result this morning. The memory regression is also ~18MB for me rather than the ~800MB you're seeing.
I commented on llvm-dev that there's an easy change that should significantly improve it. I'll look into this.
> On 21 May 2017, at 11:12, Vitaly Buka <vitalybuka at google.com> wrote:
>
> We probably should revert this and investigate compile time regression.
>
> I noticed that starting from http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1360 <http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-bootstrap/builds/1360> "build clang/msan" sometimes hangs.
>
> I bisected on my workstation using:
> BUILDBOT_CLOBBER=1 BUILDBOT_REVISION=303341 llvm/projects/zorg/zorg/buildbot/builders/sanitizers/buildbot_bootstrap.sh
>
> I noticed consistent regression on r303341. Time of "build clang/msan" increased from 8.5 min to 20 min (on 24 cores). r303341 spends a lot of time compiling just 3 files. Also I was able to reproduce this difference on ToT reverting r303341.
>
> One of the slow commands of "build clang/msan" is below.
> ToT takes 13.5 min to compile it and about 1.5Gb of RAM.
> "ToT without r303341 (reverted)" takes just 1.2 min to compile and about 0.7Gb of RAM.
>
> Also after removing -fsanitize=memory difference is about 1.4 min vs 0.3 min.
>
> /tmp/bot/llvm_build0/bin/clang-5.0 -cc1 -triple x86_64-unknown-linux-gnu -emit-obj -disable-free -main-file-name AArch64InstructionSelector.cpp -mrelocation-model pic -pic-level 2 -mthread-model posix -mdisable-fp-elim -fmath-errno -masm-verbose -mconstructor-aliases -munwind-tables -fuse-init-array -target-cpu x86-64 -momit-leaf-frame-pointer -dwarf-column-info -debug-info-kind=line-tables-only -dwarf-version=4 -debugger-tuning=gdb -ffunction-sections -fdata-sections -coverage-notes-file /tmp/bot/llvm_build_msan/lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.gcno -nostdinc++ -resource-dir /tmp/bot/llvm_build0/lib/clang/5.0.0 -dependency-file lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.o.d -sys-header-deps -MT lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.o -isystem /tmp/bot/libcxx_build_msan/include -isystem /tmp/bot/libcxx_build_msan/include/c++/v1 -D GTEST_HAS_RTTI=0 -D LLVM_BUILD_GLOBAL_ISEL -D _DEBUG -D _GNU_SOURCE -D __STDC_CONSTANT_MACROS -D __STDC_FORMAT_MACROS -D __STDC_LIMIT_MACROS -I lib/Target/AArch64 -I /tmp/bot/llvm/lib/Target/AArch64 -I include -I /tmp/bot/llvm/include -U NDEBUG -internal-isystem /usr/local/include -internal-isystem /tmp/bot/llvm_build0/lib/clang/5.0.0/include -internal-externc-isystem /usr/include/x86_64-linux-gnu -internal-externc-isystem /include -internal-externc-isystem /usr/include -O3 -Werror=date-time -Wall -W -Wno-unused-parameter -Wwrite-strings -Wcast-qual -Wmissing-field-initializers -Wno-long-long -Wcovered-switch-default -Wnon-virtual-dtor -Wdelete-non-virtual-dtor -Wstring-conversion -pedantic -w -std=c++11 -fdeprecated-macro -fdebug-compilation-dir /tmp/bot/llvm_build_msan -ferror-limit 19 -fmessage-length 0 -fvisibility-inlines-hidden -fsanitize=memory -fsanitize-blacklist=/tmp/bot/llvm_build0/lib/clang/5.0.0/msan_blacklist.txt -fno-assume-sane-operator-new -fno-rtti -fobjc-runtime=gcc -fdiagnostics-show-option -fcolor-diagnostics -vectorize-loops -vectorize-slp -o lib/Target/AArch64/CMakeFiles/LLVMAArch64CodeGen.dir/AArch64InstructionSelector.cpp.o -x c++ /tmp/bot/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
>
>
>
> On Thu, May 18, 2017 at 3:33 AM, Daniel Sanders via llvm-commits <llvm-commits at lists.llvm.org <mailto:llvm-commits at lists.llvm.org>> wrote:
> Author: dsanders
> Date: Thu May 18 05:33:36 2017
> New Revision: 303341
>
> URL: http://llvm.org/viewvc/llvm-project?rev=303341&view=rev <http://llvm.org/viewvc/llvm-project?rev=303341&view=rev>
> Log:
> Re-commit: [globalisel][tablegen] Import rules containing intrinsic_wo_chain.
>
> Summary:
> As of this patch, 1018 out of 3938 rules are currently imported.
>
> Depends on D32275
>
> Reviewers: qcolombet, kristof.beyls, rovka, t.p.northover, ab, aditya_nandakumar
>
> Reviewed By: qcolombet
>
> Subscribers: dberris, igorb, llvm-commits
>
> Differential Revision: https://reviews.llvm.org/D32278 <https://reviews.llvm.org/D32278>
>
> The previous commit failed on test-suite/Bitcode/simd_ops/AArch64_halide_runtime.bc
> because isImmOperandEqual() assumed MO was a register operand and that's not
> always true.
>
>
> Modified:
> llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
> llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp
> llvm/trunk/test/TableGen/GlobalISelEmitter.td
> llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
>
> Modified: llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td?rev=303341&r1=303340&r2=303341&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td?rev=303341&r1=303340&r2=303341&view=diff>
> ==============================================================================
> --- llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td (original)
> +++ llvm/trunk/include/llvm/Target/GlobalISel/SelectionDAGCompat.td Thu May 18 05:33:36 2017
> @@ -62,6 +62,7 @@ def : GINodeEquiv<G_FMUL, fmul>;
> def : GINodeEquiv<G_FDIV, fdiv>;
> def : GINodeEquiv<G_FREM, frem>;
> def : GINodeEquiv<G_FPOW, fpow>;
> +def : GINodeEquiv<G_INTRINSIC, intrinsic_wo_chain>;
> def : GINodeEquiv<G_BR, br>;
>
> // Specifies the GlobalISel equivalents for SelectionDAG's ComplexPattern.
>
> Modified: llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp?rev=303341&r1=303340&r2=303341&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp?rev=303341&r1=303340&r2=303341&view=diff>
> ==============================================================================
> --- llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp (original)
> +++ llvm/trunk/lib/CodeGen/GlobalISel/InstructionSelector.cpp Thu May 18 05:33:36 2017
> @@ -73,7 +73,7 @@ bool InstructionSelector::isOperandImmEq
> const MachineOperand &MO, int64_t Value,
> const MachineRegisterInfo &MRI) const {
>
> - if (MO.getReg())
> + if (MO.isReg() && MO.getReg())
> if (auto VRegVal = getConstantVRegVal(MO.getReg(), MRI))
> return *VRegVal == Value;
> return false;
>
> Modified: llvm/trunk/test/TableGen/GlobalISelEmitter.td
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=303341&r1=303340&r2=303341&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/test/TableGen/GlobalISelEmitter.td?rev=303341&r1=303340&r2=303341&view=diff>
> ==============================================================================
> --- llvm/trunk/test/TableGen/GlobalISelEmitter.td (original)
> +++ llvm/trunk/test/TableGen/GlobalISelEmitter.td Thu May 18 05:33:36 2017
> @@ -7,6 +7,10 @@ include "llvm/Target/Target.td"
> def MyTargetISA : InstrInfo;
> def MyTarget : Target { let InstructionSet = MyTargetISA; }
>
> +let TargetPrefix = "mytarget" in {
> +def int_mytarget_nop : Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem]>;
> +}
> +
> def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
> def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
> def GPR32Op : RegisterOperand<GPR32>;
> @@ -127,6 +131,37 @@ def : Pat<(select GPR32:$src1, complex:$
> def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2),
> [(set GPR32:$dst, (add GPR32:$src1, GPR32:$src2))]>;
>
> +//===- Test a simple pattern with an intrinsic. ---------------------------===//
> +//
> +
> +// CHECK-LABEL: if ([&]() {
> +// CHECK-NEXT: MachineInstr &MI0 = I;
> +// CHECK-NEXT: if (MI0.getNumOperands() < 3)
> +// CHECK-NEXT: return false;
> +// CHECK-NEXT: if ((MI0.getOpcode() == TargetOpcode::G_INTRINSIC) &&
> +// CHECK-NEXT: ((/* dst */ (MRI.getType(MI0.getOperand(0).getReg()) == (LLT::scalar(32))) &&
> +// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(0).getReg(), MRI, TRI))))) &&
> +// CHECK-NEXT: ((/* Operand 1 */ (isOperandImmEqual(MI0.getOperand(1), [[ID:[0-9]+]], MRI)))) &&
> +// CHECK-NEXT: ((/* src1 */ (MRI.getType(MI0.getOperand(2).getReg()) == (LLT::scalar(32))) &&
> +// CHECK-NEXT: ((&RBI.getRegBankFromRegClass(MyTarget::GPR32RegClass) == RBI.getRegBank(MI0.getOperand(2).getReg(), MRI, TRI)))))) {
> +// CHECK-NEXT: // (intrinsic_wo_chain:i32 [[ID]]:iPTR, GPR32:i32:$src1) => (MOV:i32 GPR32:i32:$src1)
> +// CHECK-NEXT: MachineInstrBuilder MIB = BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(MyTarget::MOV));
> +// CHECK-NEXT: MIB.add(MI0.getOperand(0)/*dst*/);
> +// CHECK-NEXT: MIB.add(MI0.getOperand(2)/*src1*/);
> +// CHECK-NEXT: for (const auto *FromMI : {&MI0, })
> +// CHECK-NEXT: for (const auto &MMO : FromMI->memoperands())
> +// CHECK-NEXT: MIB.addMemOperand(MMO);
> +// CHECK-NEXT: I.eraseFromParent();
> +// CHECK-NEXT: MachineInstr &NewI = *MIB;
> +// CHECK-NEXT: constrainSelectedInstRegOperands(NewI, TII, TRI, RBI);
> +// CHECK-NEXT: return true;
> +// CHECK-NEXT: }
> +// CHECK-NEXT: return false;
> +// CHECK-NEXT: }()) { return true; }
> +
> +def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1),
> + [(set GPR32:$dst, (int_mytarget_nop GPR32:$src1))]>;
> +
> //===- Test a nested instruction match. -----------------------------------===//
>
> // CHECK-LABEL: if ([&]() {
>
> Modified: llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp
> URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=303341&r1=303340&r2=303341&view=diff <http://llvm.org/viewvc/llvm-project/llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp?rev=303341&r1=303340&r2=303341&view=diff>
> ==============================================================================
> --- llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp (original)
> +++ llvm/trunk/utils/TableGen/GlobalISelEmitter.cpp Thu May 18 05:33:36 2017
> @@ -1325,8 +1325,27 @@ Expected<InstructionMatcher &> GlobalISe
>
> // Match the used operands (i.e. the children of the operator).
> for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {
> - if (auto Error = importChildMatcher(InsnMatcher, Src->getChild(i), OpIdx++,
> - TempOpIdx))
> + TreePatternNode *SrcChild = Src->getChild(i);
> +
> + // For G_INTRINSIC, the operand immediately following the defs is an
> + // intrinsic ID.
> + if (SrcGI.TheDef->getName() == "G_INTRINSIC" && i == 0) {
> + if (!SrcChild->isLeaf())
> + return failedImport("Expected IntInit containing intrinsic ID");
> +
> + if (IntInit *SrcChildIntInit =
> + dyn_cast<IntInit>(SrcChild->getLeafValue())) {
> + OperandMatcher &OM =
> + InsnMatcher.addOperand(OpIdx++, SrcChild->getName(), TempOpIdx);
> + OM.addPredicate<IntOperandMatcher>(SrcChildIntInit->getValue());
> + continue;
> + }
> +
> + return failedImport("Expected IntInit containing instrinsic ID)");
> + }
> +
> + if (auto Error =
> + importChildMatcher(InsnMatcher, SrcChild, OpIdx++, TempOpIdx))
> return std::move(Error);
> }
>
> @@ -1361,7 +1380,7 @@ Error GlobalISelEmitter::importChildMatc
>
> auto OpTyOrNone = MVTToLLT(ChildTypes.front().getConcrete());
> if (!OpTyOrNone)
> - return failedImport("Src operand has an unsupported type");
> + return failedImport("Src operand has an unsupported type (" + to_string(*SrcChild) + ")");
> OM.addPredicate<LLTOperandMatcher>(*OpTyOrNone);
>
> // Check for nested instructions.
>
>
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