[PATCH] D33188: [X86][AVX512] Improve lowering of AVX512 compare intrinsics (remove redundant shift left+right instructions).

[Igor Breger via Phabricator via llvm-commits]

igorb added a comment.

I think we need more generic solution, that latter could be expended to to other vxi1 types and improve cases like

      t44: v8i1 = X86ISD::CMPM t2, t4, Constant:i8<17>
      t45: i8 = bitcast t44
    t14: i16 = zero_extend t45
  t32: v16i1 = bitcast t14

The relevant CONCAT_VECTORS implemented by insert_subvector, please move the implementation to insert1BitVector().
Would you consider to try the follow approach.

  Detect that we have  insert_subvector zero, CMPM  or  insert_subvector zero, (AND  CMPM, MASK) , etc .. case and mark it legal.    
  In td file define new instructions without DAG patterns.
  add lower patters to map    
                   insert_subvector zeroVec,  CMP_DAG    ->  CMPM_NEW instructions



================
Comment at: lib/Target/X86/X86InstrAVX512.td:1822
   // Accept explicit immediate argument form instead of comparison code.
   let isAsmParserOnly = 1, hasSideEffects = 0 in {
     def rri_alt : AVX512AIi8<opc, MRMSrcReg,
----------------
this part now has isCodeGenOnly= 1 and isAsmParserOnly = 1 , please check the result of tabel-gen


https://reviews.llvm.org/D33188