[PATCH] D32737: [Constants][SVE] Represent the runtime length of a scalable vector

[Chandler Carruth via Phabricator via llvm-commits]

chandlerc added a comment.

In https://reviews.llvm.org/D32737#759325, @rengolin wrote:

> @echristo @chandlerc @lattner @majnemer Ping.
>
> This is a trivial change, discussed in the past, and I'm inclined to approve.


Uh, where was it discussed? It's entirely possible I missed it, but I can't find any consensus on any of the threads that we actually want to support runtime vector width in LLVM's IR.

The most recent thread I find on llvm-dev is from Mar 7: "[llvm-dev][RFC][SVE] Extend vector types to support SVE registers."

That thread exclusively talks about MVT and the code generator. I don't see its relevance to the IR.

Before taht we have the big RFC for SVE. And there, I had suggested in November of last year to get a fresh RFC which I don't see having happened yet.

And in response to that you indicated the patches under review were just examples, not planning to be committed.

If I missed the RFC, totally my bad, but I did search for 'SVE llvm-dev' and was unable to find it, so I suspect I may not be the only one that has continued to wait for an actual follow-up RFC.

For the record, I remain unconvinced that LLVM's IR should support non-constant vector widths. I understand why some CPU vendors are interested in this, but the motivation for LLVM to support it so far is very weak, and the cost in terms of complexity to the IR and every vector-aware optimization is, in my opinion, far too high. However, I'm trying to remain open about this subject and have been awaiting a fresh RFC on llvm-dev to really dig into the motivation.


https://reviews.llvm.org/D32737