[PATCH] D33367: [AMDGPU] Narrow lshl from 64 to 32 bit if possible

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, kzhuravl.

Turn expensive 64 bit shift into 32 bit if shift does not overflow int:
shl (ext x) => zext (shl x)


Repository:
  rL LLVM

https://reviews.llvm.org/D33367

Files:
  lib/Target/AMDGPU/AMDGPUISelLowering.cpp
  test/CodeGen/AMDGPU/add.i16.ll
  test/CodeGen/AMDGPU/add.v2i16.ll
  test/CodeGen/AMDGPU/bfe-patterns.ll
  test/CodeGen/AMDGPU/ctlz.ll
  test/CodeGen/AMDGPU/ctlz_zero_undef.ll
  test/CodeGen/AMDGPU/ds_write2.ll
  test/CodeGen/AMDGPU/fmed3.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll
  test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
  test/CodeGen/AMDGPU/lshl64-to-32.ll
  test/CodeGen/AMDGPU/shift-and-i64-ubfe.ll
  test/CodeGen/AMDGPU/srl.ll
  test/CodeGen/AMDGPU/sub.i16.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D33367.99620.patch
Type: text/x-patch
Size: 15102 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170519/3db18dbc/attachment.bin>