[PATCH] D33312: [Sparc] Do not encode the 2 LSBs of the address in the call instruction

[Daniel Cederman via Phabricator via llvm-commits]

dcederman created this revision.

https://reviews.llvm.org/D33312

Files:
  lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
  test/MC/Sparc/sparc-ctrl-instructions.s


Index: test/MC/Sparc/sparc-ctrl-instructions.s
===================================================================
--- test/MC/Sparc/sparc-ctrl-instructions.s
+++ test/MC/Sparc/sparc-ctrl-instructions.s
@@ -14,6 +14,9 @@
         ! CHECK: call %g1     ! encoding: [0x9f,0xc0,0x40,0x00]
         call %g1
 
+        ! CHECK: call 1234    ! encoding: [0x40,0x00,0x01,0x34]
+        call 1234
+
         ! CHECK: call %g1+%lo(sym)   ! encoding: [0x9f,0xc0,0b011000AA,A]
         ! CHECK-NEXT:                ! fixup A - offset: 0, value: %lo(sym), kind: fixup_sparc_lo10
         call %g1+%lo(sym)
Index: lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
===================================================================
--- lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
+++ lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp
@@ -156,7 +156,9 @@
                      SmallVectorImpl<MCFixup> &Fixups,
                      const MCSubtargetInfo &STI) const {
   const MCOperand &MO = MI.getOperand(OpNo);
-  if (MO.isReg() || MO.isImm())
+  if (MO.isImm())
+    return MO.getImm() >> 2;
+  if (MO.isReg())
     return getMachineOpValue(MI, MO, Fixups, STI);
 
   if (MI.getOpcode() == SP::TLS_CALL) {


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