[llvm] r303305 - AMDGPU: Remove old intrinsic uses

[Matt Arsenault via llvm-commits]

Author: arsenm
Date: Wed May 17 16:38:21 2017
New Revision: 303305

URL: http://llvm.org/viewvc/llvm-project?rev=303305&view=rev
Log:
AMDGPU: Remove old intrinsic uses

Modified:
    llvm/trunk/test/CodeGen/AMDGPU/coalescer_distribute.ll
    llvm/trunk/test/CodeGen/AMDGPU/endcf-loop-header.ll
    llvm/trunk/test/CodeGen/AMDGPU/i1-copy-phi.ll
    llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
    llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll

Modified: llvm/trunk/test/CodeGen/AMDGPU/coalescer_distribute.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/coalescer_distribute.ll?rev=303305&r1=303304&r2=303305&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/coalescer_distribute.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/coalescer_distribute.ll Wed May 17 16:38:21 2017
@@ -5,7 +5,7 @@ target triple = "amdgcn--"
 
 define spir_kernel void @hoge() {
 bb:
-  %tmp = tail call i32 @llvm.r600.read.tidig.x()
+  %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
   br i1 undef, label %bb2, label %bb23
 
 bb2:
@@ -50,4 +50,4 @@ bb34:
   ret void
 }
 
-declare i32 @llvm.r600.read.tidig.x()
+declare i32 @llvm.amdgcn.workitem.id.x()

Modified: llvm/trunk/test/CodeGen/AMDGPU/endcf-loop-header.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/endcf-loop-header.ll?rev=303305&r1=303304&r2=303305&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/endcf-loop-header.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/endcf-loop-header.ll Wed May 17 16:38:21 2017
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=amdgcn -mcpu=SI -verify-machineinstrs | FileCheck %s
+; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s
 
 ; This tests that the llvm.SI.end.cf intrinsic is not inserted into the
 ; loop block.  This intrinsic will be lowered to s_or_b64 by the code
@@ -14,7 +14,7 @@
 ; CHECK: s_cbranch_execnz [[LOOP_LABEL]]
 define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
 entry:
-  %cond = call i32 @llvm.r600.read.tidig.x() #0
+  %cond = call i32 @llvm.amdgcn.workitem.id.x() #0
   %tmp0 = icmp eq i32 %cond, 0
   br i1 %tmp0, label %if, label %loop
 
@@ -34,6 +34,6 @@ done:
   ret void
 }
 
-declare i32 @llvm.r600.read.tidig.x() #0
+declare i32 @llvm.amdgcn.workitem.id.x() #0
 
-attributes #0 = { readnone }
+attributes #0 = { nounwind readnone }

Modified: llvm/trunk/test/CodeGen/AMDGPU/i1-copy-phi.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/i1-copy-phi.ll?rev=303305&r1=303304&r2=303305&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/i1-copy-phi.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/i1-copy-phi.ll Wed May 17 16:38:21 2017
@@ -12,7 +12,7 @@
 ; SI: s_endpgm
 define amdgpu_kernel void @br_i1_phi(i32 %arg) {
 bb:
-  %tidig = call i32 @llvm.r600.read.tidig.x() #0
+  %tidig = call i32 @llvm.amdgcn.workitem.id.x()
   %cmp = trunc i32 %tidig to i1
   br i1 %cmp, label %bb2, label %bb3
 
@@ -32,6 +32,6 @@ bb6:
   ret void
 }
 
-declare i32 @llvm.r600.read.tidig.x() #0
+declare i32 @llvm.amdgcn.workitem.id.x() #0
 
-attributes #0 = { readnone }
+attributes #0 = { nounwind readnone }

Modified: llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll?rev=303305&r1=303304&r2=303305&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/llvm.amdgcn.s.barrier.ll Wed May 17 16:38:21 2017
@@ -7,14 +7,13 @@
 ; GFX9: flat_store_dword
 ; GFX9-NOT: s_waitcnt
 ; GCN: s_barrier
-define amdgpu_kernel void @test_barrier(i32 addrspace(1)* %out) #0 {
+define amdgpu_kernel void @test_barrier(i32 addrspace(1)* %out, i32 %size) #0 {
 entry:
   %tmp = call i32 @llvm.amdgcn.workitem.id.x()
   %tmp1 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp
   store i32 %tmp, i32 addrspace(1)* %tmp1
   call void @llvm.amdgcn.s.barrier()
-  %tmp2 = call i32 @llvm.r600.read.local.size.x()
-  %tmp3 = sub i32 %tmp2, 1
+  %tmp3 = sub i32 %size, 1
   %tmp4 = sub i32 %tmp3, %tmp
   %tmp5 = getelementptr i32, i32 addrspace(1)* %out, i32 %tmp4
   %tmp6 = load i32, i32 addrspace(1)* %tmp5
@@ -24,7 +23,6 @@ entry:
 
 declare void @llvm.amdgcn.s.barrier() #1
 declare i32 @llvm.amdgcn.workitem.id.x() #2
-declare i32 @llvm.r600.read.local.size.x() #2
 
 attributes #0 = { nounwind }
 attributes #1 = { convergent nounwind }

Modified: llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll?rev=303305&r1=303304&r2=303305&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll (original)
+++ llvm/trunk/test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot-compute.ll Wed May 17 16:38:21 2017
@@ -186,7 +186,7 @@ bb12:
   %tmp140 = phi float [ 0.000000e+00, %bb ], [ %tmp405, %bb145 ]
   %tmp141 = phi float [ 0.000000e+00, %bb ], [ %tmp406, %bb145 ]
   %tmp142 = bitcast float %tmp95 to i32
-  %tid = call i32 @llvm.r600.read.tidig.x() #1
+  %tid = call i32 @llvm.amdgcn.workitem.id.x() #1
   %tmp143 = icmp sgt i32 %tmp142, %tid
   br i1 %tmp143, label %bb144, label %bb145
 
@@ -593,7 +593,7 @@ bb145:
   br label %bb12
 }
 
-declare i32 @llvm.r600.read.tidig.x() #1
+declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 attributes #0 = { nounwind }
 attributes #1 = { nounwind readnone }