[PATCH] D33248: [Power9] Exploit D-form vector load/store

[Tim Shen via Phabricator via llvm-commits]

timshen accepted this revision.
timshen added inline comments.
This revision is now accepted and ready to land.


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Comment at: lib/Target/PowerPC/PPCInstrVSX.td:2516
+
+  def : Pat<(v2f64 (load xaddr:$src)), (LXVX xaddr:$src)>;
+  def : Pat<(v2i64 (load xaddr:$src)), (LXVX xaddr:$src)>;
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syzaara wrote:
> timshen wrote:
> > Why xoaddr -> xaddr change? AFAIK LXVX doesn't accept immediates, does it?
> LXVX doesn't accept immediates, but the addressing mode xaddr checks if this instruction can be better represented with a register + immediate rather than register + register. Since we now have a d-form instruction, LXVX can be changed to xaddr and if the register + immediate is possible, it will be changed to used LXV. With xoaddr, only register + register is used, even if the input is an immediate.
I see, thanks for the explanation!

My understanding is that there are passes that generates LXVX without necessarily going through an ISD::LOAD, and we want to optimize for those as well.


https://reviews.llvm.org/D33248