[llvm] r303169 - [GlobalISel][X86] Split memop test file. NFC
Igor Breger via llvm-commits
llvm-commits at lists.llvm.org
Tue May 16 06:37:31 PDT 2017
Author: ibreger
Date: Tue May 16 08:37:31 2017
New Revision: 303169
URL: http://llvm.org/viewvc/llvm-project?rev=303169&view=rev
Log:
[GlobalISel][X86] Split memop test file. NFC
Added:
llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll
- copied, changed from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar.ll
- copied, changed from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/memop-vec.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir
- copied, changed from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir
- copied, changed from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
Removed:
llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir
llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir
Copied: llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll (from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll?p2=llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar-x32.ll&p1=llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll&r1=303165&r2=303169&rev=303169&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar.ll (from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar.ll?p2=llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar.ll&p1=llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll&r1=303165&r2=303169&rev=303169&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/memop-scalar.ll Tue May 16 08:37:31 2017
@@ -1,13 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_GREEDY
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX_GREEDY
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512F_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512F_GREEDY
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512VL_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512VL_GREEDY
-
+; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_FAST
+; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE_GREEDY
define i8 @test_load_i8(i8 * %p1) {
; ALL-LABEL: test_load_i8:
@@ -77,34 +70,6 @@ define double @test_load_double(double *
ret double %r
}
-define <4 x i32> @test_load_v4i32_noalign(<4 x i32> * %p1) {
-; SSE-LABEL: test_load_v4i32_noalign:
-; SSE: # BB#0:
-; SSE-NEXT: movups (%rdi), %xmm0
-; SSE-NEXT: retq
-;
-; ALL_AVX-LABEL: test_load_v4i32_noalign:
-; ALL_AVX: # BB#0:
-; ALL_AVX-NEXT: vmovups (%rdi), %xmm0
-; ALL_AVX-NEXT: retq
- %r = load <4 x i32>, <4 x i32>* %p1, align 1
- ret <4 x i32> %r
-}
-
-define <4 x i32> @test_load_v4i32_align(<4 x i32> * %p1) {
-; SSE-LABEL: test_load_v4i32_align:
-; SSE: # BB#0:
-; SSE-NEXT: movaps (%rdi), %xmm0
-; SSE-NEXT: retq
-;
-; ALL_AVX-LABEL: test_load_v4i32_align:
-; ALL_AVX: # BB#0:
-; ALL_AVX-NEXT: vmovaps (%rdi), %xmm0
-; ALL_AVX-NEXT: retq
- %r = load <4 x i32>, <4 x i32>* %p1, align 16
- ret <4 x i32> %r
-}
-
define i32 * @test_store_i32(i32 %val, i32 * %p1) {
; ALL-LABEL: test_store_i32:
; ALL: # BB#0:
@@ -139,19 +104,6 @@ define float * @test_store_float(float %
; SSE_GREEDY-NEXT: movss %xmm0, (%rdi)
; SSE_GREEDY-NEXT: movq %rdi, %rax
; SSE_GREEDY-NEXT: retq
-;
-; ALL_AVX_FAST-LABEL: test_store_float:
-; ALL_AVX_FAST: # BB#0:
-; ALL_AVX_FAST-NEXT: vmovd %xmm0, %eax
-; ALL_AVX_FAST-NEXT: movl %eax, (%rdi)
-; ALL_AVX_FAST-NEXT: movq %rdi, %rax
-; ALL_AVX_FAST-NEXT: retq
-;
-; ALL_AVX_GREEDY-LABEL: test_store_float:
-; ALL_AVX_GREEDY: # BB#0:
-; ALL_AVX_GREEDY-NEXT: vmovss %xmm0, (%rdi)
-; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
-; ALL_AVX_GREEDY-NEXT: retq
store float %val, float* %p1
ret float * %p1;
}
@@ -171,18 +123,6 @@ define double * @test_store_double(doubl
; SSE_GREEDY-NEXT: movq %rdi, %rax
; SSE_GREEDY-NEXT: retq
;
-; ALL_AVX_FAST-LABEL: test_store_double:
-; ALL_AVX_FAST: # BB#0:
-; ALL_AVX_FAST-NEXT: vmovq %xmm0, %rax
-; ALL_AVX_FAST-NEXT: movq %rax, (%rdi)
-; ALL_AVX_FAST-NEXT: movq %rdi, %rax
-; ALL_AVX_FAST-NEXT: retq
-;
-; ALL_AVX_GREEDY-LABEL: test_store_double:
-; ALL_AVX_GREEDY: # BB#0:
-; ALL_AVX_GREEDY-NEXT: vmovsd %xmm0, (%rdi)
-; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
-; ALL_AVX_GREEDY-NEXT: retq
store double %val, double* %p1
ret double * %p1;
}
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/memop-vec.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/memop-vec.ll?rev=303169&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/memop-vec.ll (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/memop-vec.ll Tue May 16 08:37:31 2017
@@ -0,0 +1,39 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX
+; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=skx -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SKX
+
+define <4 x i32> @test_load_v4i32_noalign(<4 x i32> * %p1) {
+; ALL-LABEL: test_load_v4i32_noalign:
+; ALL: # BB#0:
+; ALL-NEXT: vmovups (%rdi), %xmm0
+; ALL-NEXT: retq
+ %r = load <4 x i32>, <4 x i32>* %p1, align 1
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @test_load_v4i32_align(<4 x i32> * %p1) {
+; ALL-LABEL: test_load_v4i32_align:
+; ALL: # BB#0:
+; ALL-NEXT: vmovaps (%rdi), %xmm0
+; ALL-NEXT: retq
+ %r = load <4 x i32>, <4 x i32>* %p1, align 16
+ ret <4 x i32> %r
+}
+
+define void @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
+; ALL-LABEL: test_store_v4i32_noalign:
+; ALL: # BB#0:
+; ALL-NEXT: vmovups %xmm0, (%rdi)
+; ALL-NEXT: retq
+ store <4 x i32> %val, <4 x i32>* %p1, align 1
+ ret void
+}
+
+define void @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
+; ALL-LABEL: test_store_v4i32_align:
+; ALL: # BB#0:
+; ALL-NEXT: vmovaps %xmm0, (%rdi)
+; ALL-NEXT: retq
+ store <4 x i32> %val, <4 x i32>* %p1, align 16
+ ret void
+}
Removed: llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll?rev=303168&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/memop-x32.ll (removed)
@@ -1,101 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=i386-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_FAST
-; RUN: llc -mtriple=i386-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_GREEDY
-
-;TODO merge with x86-64 tests (many operations not suppored yet)
-
-define i8 @test_load_i8(i8 * %p1) {
-; ALL-LABEL: test_load_i8:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: movb (%eax), %al
-; ALL-NEXT: retl
- %r = load i8, i8* %p1
- ret i8 %r
-}
-
-define i16 @test_load_i16(i16 * %p1) {
-; ALL-LABEL: test_load_i16:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: movzwl (%eax), %eax
-; ALL-NEXT: retl
- %r = load i16, i16* %p1
- ret i16 %r
-}
-
-define i32 @test_load_i32(i32 * %p1) {
-; ALL-LABEL: test_load_i32:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: retl
- %r = load i32, i32* %p1
- ret i32 %r
-}
-
-define i8 * @test_store_i8(i8 %val, i8 * %p1) {
-; ALL-LABEL: test_store_i8:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movb (%eax), %cl
-; ALL-NEXT: leal 8(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: movb %cl, (%eax)
-; ALL-NEXT: retl
- store i8 %val, i8* %p1
- ret i8 * %p1;
-}
-
-define i16 * @test_store_i16(i16 %val, i16 * %p1) {
-; ALL-LABEL: test_store_i16:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movzwl (%eax), %ecx
-; ALL-NEXT: leal 8(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: movw %cx, (%eax)
-; ALL-NEXT: retl
- store i16 %val, i16* %p1
- ret i16 * %p1;
-}
-
-define i32 * @test_store_i32(i32 %val, i32 * %p1) {
-; ALL-LABEL: test_store_i32:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movl (%eax), %ecx
-; ALL-NEXT: leal 8(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: movl %ecx, (%eax)
-; ALL-NEXT: retl
- store i32 %val, i32* %p1
- ret i32 * %p1;
-}
-
-define i32* @test_load_ptr(i32** %ptr1) {
-; ALL-LABEL: test_load_ptr:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: retl
- %p = load i32*, i32** %ptr1
- ret i32* %p
-}
-
-define void @test_store_ptr(i32** %ptr1, i32* %a) {
-; ALL-LABEL: test_store_ptr:
-; ALL: # BB#0:
-; ALL-NEXT: leal 4(%esp), %eax
-; ALL-NEXT: movl (%eax), %eax
-; ALL-NEXT: leal 8(%esp), %ecx
-; ALL-NEXT: movl (%ecx), %ecx
-; ALL-NEXT: movl %ecx, (%eax)
-; ALL-NEXT: retl
- store i32* %a, i32** %ptr1
- ret void
-}
Removed: llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll?rev=303168&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/memop.ll (removed)
@@ -1,206 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=x86_64-linux-gnu -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE_GREEDY
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX_GREEDY
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512F_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512F_GREEDY
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_FAST --check-prefix=AVX512VL_FAST
-; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -regbankselect-greedy -global-isel < %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=ALL_AVX --check-prefix=ALL_AVX_GREEDY --check-prefix=AVX512VL_GREEDY
-
-
-define i8 @test_load_i8(i8 * %p1) {
-; ALL-LABEL: test_load_i8:
-; ALL: # BB#0:
-; ALL-NEXT: movb (%rdi), %al
-; ALL-NEXT: retq
- %r = load i8, i8* %p1
- ret i8 %r
-}
-
-define i16 @test_load_i16(i16 * %p1) {
-; ALL-LABEL: test_load_i16:
-; ALL: # BB#0:
-; ALL-NEXT: movzwl (%rdi), %eax
-; ALL-NEXT: retq
- %r = load i16, i16* %p1
- ret i16 %r
-}
-
-define i32 @test_load_i32(i32 * %p1) {
-; ALL-LABEL: test_load_i32:
-; ALL: # BB#0:
-; ALL-NEXT: movl (%rdi), %eax
-; ALL-NEXT: retq
- %r = load i32, i32* %p1
- ret i32 %r
-}
-
-define i64 @test_load_i64(i64 * %p1) {
-; ALL-LABEL: test_load_i64:
-; ALL: # BB#0:
-; ALL-NEXT: movq (%rdi), %rax
-; ALL-NEXT: retq
- %r = load i64, i64* %p1
- ret i64 %r
-}
-
-define float @test_load_float(float * %p1) {
-; SSE-LABEL: test_load_float:
-; SSE: # BB#0:
-; SSE-NEXT: movl (%rdi), %eax
-; SSE-NEXT: movd %eax, %xmm0
-; SSE-NEXT: retq
-;
-; ALL_AVX-LABEL: test_load_float:
-; ALL_AVX: # BB#0:
-; ALL_AVX-NEXT: movl (%rdi), %eax
-; ALL_AVX-NEXT: vmovd %eax, %xmm0
-; ALL_AVX-NEXT: retq
- %r = load float, float* %p1
- ret float %r
-}
-
-define double @test_load_double(double * %p1) {
-; SSE-LABEL: test_load_double:
-; SSE: # BB#0:
-; SSE-NEXT: movq (%rdi), %rax
-; SSE-NEXT: movq %rax, %xmm0
-; SSE-NEXT: retq
-;
-; ALL_AVX-LABEL: test_load_double:
-; ALL_AVX: # BB#0:
-; ALL_AVX-NEXT: movq (%rdi), %rax
-; ALL_AVX-NEXT: vmovq %rax, %xmm0
-; ALL_AVX-NEXT: retq
- %r = load double, double* %p1
- ret double %r
-}
-
-define <4 x i32> @test_load_v4i32_noalign(<4 x i32> * %p1) {
-; SSE-LABEL: test_load_v4i32_noalign:
-; SSE: # BB#0:
-; SSE-NEXT: movups (%rdi), %xmm0
-; SSE-NEXT: retq
-;
-; ALL_AVX-LABEL: test_load_v4i32_noalign:
-; ALL_AVX: # BB#0:
-; ALL_AVX-NEXT: vmovups (%rdi), %xmm0
-; ALL_AVX-NEXT: retq
- %r = load <4 x i32>, <4 x i32>* %p1, align 1
- ret <4 x i32> %r
-}
-
-define <4 x i32> @test_load_v4i32_align(<4 x i32> * %p1) {
-; SSE-LABEL: test_load_v4i32_align:
-; SSE: # BB#0:
-; SSE-NEXT: movaps (%rdi), %xmm0
-; SSE-NEXT: retq
-;
-; ALL_AVX-LABEL: test_load_v4i32_align:
-; ALL_AVX: # BB#0:
-; ALL_AVX-NEXT: vmovaps (%rdi), %xmm0
-; ALL_AVX-NEXT: retq
- %r = load <4 x i32>, <4 x i32>* %p1, align 16
- ret <4 x i32> %r
-}
-
-define i32 * @test_store_i32(i32 %val, i32 * %p1) {
-; ALL-LABEL: test_store_i32:
-; ALL: # BB#0:
-; ALL-NEXT: movl %edi, (%rsi)
-; ALL-NEXT: movq %rsi, %rax
-; ALL-NEXT: retq
- store i32 %val, i32* %p1
- ret i32 * %p1;
-}
-
-define i64 * @test_store_i64(i64 %val, i64 * %p1) {
-; ALL-LABEL: test_store_i64:
-; ALL: # BB#0:
-; ALL-NEXT: movq %rdi, (%rsi)
-; ALL-NEXT: movq %rsi, %rax
-; ALL-NEXT: retq
- store i64 %val, i64* %p1
- ret i64 * %p1;
-}
-
-define float * @test_store_float(float %val, float * %p1) {
-;
-; SSE_FAST-LABEL: test_store_float:
-; SSE_FAST: # BB#0:
-; SSE_FAST-NEXT: movd %xmm0, %eax
-; SSE_FAST-NEXT: movl %eax, (%rdi)
-; SSE_FAST-NEXT: movq %rdi, %rax
-; SSE_FAST-NEXT: retq
-;
-; SSE_GREEDY-LABEL: test_store_float:
-; SSE_GREEDY: # BB#0:
-; SSE_GREEDY-NEXT: movss %xmm0, (%rdi)
-; SSE_GREEDY-NEXT: movq %rdi, %rax
-; SSE_GREEDY-NEXT: retq
-;
-; ALL_AVX_FAST-LABEL: test_store_float:
-; ALL_AVX_FAST: # BB#0:
-; ALL_AVX_FAST-NEXT: vmovd %xmm0, %eax
-; ALL_AVX_FAST-NEXT: movl %eax, (%rdi)
-; ALL_AVX_FAST-NEXT: movq %rdi, %rax
-; ALL_AVX_FAST-NEXT: retq
-;
-; ALL_AVX_GREEDY-LABEL: test_store_float:
-; ALL_AVX_GREEDY: # BB#0:
-; ALL_AVX_GREEDY-NEXT: vmovss %xmm0, (%rdi)
-; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
-; ALL_AVX_GREEDY-NEXT: retq
- store float %val, float* %p1
- ret float * %p1;
-}
-
-define double * @test_store_double(double %val, double * %p1) {
-;
-; SSE_FAST-LABEL: test_store_double:
-; SSE_FAST: # BB#0:
-; SSE_FAST-NEXT: movq %xmm0, %rax
-; SSE_FAST-NEXT: movq %rax, (%rdi)
-; SSE_FAST-NEXT: movq %rdi, %rax
-; SSE_FAST-NEXT: retq
-;
-; SSE_GREEDY-LABEL: test_store_double:
-; SSE_GREEDY: # BB#0:
-; SSE_GREEDY-NEXT: movsd %xmm0, (%rdi)
-; SSE_GREEDY-NEXT: movq %rdi, %rax
-; SSE_GREEDY-NEXT: retq
-;
-; ALL_AVX_FAST-LABEL: test_store_double:
-; ALL_AVX_FAST: # BB#0:
-; ALL_AVX_FAST-NEXT: vmovq %xmm0, %rax
-; ALL_AVX_FAST-NEXT: movq %rax, (%rdi)
-; ALL_AVX_FAST-NEXT: movq %rdi, %rax
-; ALL_AVX_FAST-NEXT: retq
-;
-; ALL_AVX_GREEDY-LABEL: test_store_double:
-; ALL_AVX_GREEDY: # BB#0:
-; ALL_AVX_GREEDY-NEXT: vmovsd %xmm0, (%rdi)
-; ALL_AVX_GREEDY-NEXT: movq %rdi, %rax
-; ALL_AVX_GREEDY-NEXT: retq
- store double %val, double* %p1
- ret double * %p1;
-}
-
-define i32* @test_load_ptr(i32** %ptr1) {
-; ALL-LABEL: test_load_ptr:
-; ALL: # BB#0:
-; ALL-NEXT: movq (%rdi), %rax
-; ALL-NEXT: retq
- %p = load i32*, i32** %ptr1
- ret i32* %p
-}
-
-define void @test_store_ptr(i32** %ptr1, i32* %a) {
-; ALL-LABEL: test_store_ptr:
-; ALL: # BB#0:
-; ALL-NEXT: movq %rsi, (%rdi)
-; ALL-NEXT: retq
- store i32* %a, i32** %ptr1
- ret void
-}
Copied: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir (from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir?p2=llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar-x32.mir&p1=llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir&r1=303165&r2=303169&rev=303169&view=diff
==============================================================================
(empty)
Copied: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir (from r303165, llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir)
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir?p2=llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir&p1=llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir&r1=303165&r2=303169&rev=303169&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-scalar.mir Tue May 16 08:37:31 2017
@@ -34,7 +34,6 @@
ret float %r
}
-
define double @test_load_double(double* %p1) {
%r = load double, double* %p1
ret double %r
@@ -45,16 +44,6 @@
ret double %r
}
- define <4 x i32> @test_load_v4i32_noalign(<4 x i32>* %p1) {
- %r = load <4 x i32>, <4 x i32>* %p1, align 1
- ret <4 x i32> %r
- }
-
- define <4 x i32> @test_load_v4i32_align(<4 x i32>* %p1) {
- %r = load <4 x i32>, <4 x i32>* %p1, align 16
- ret <4 x i32> %r
- }
-
define i32* @test_store_i32(i32 %val, i32* %p1) {
store i32 %val, i32* %p1
ret i32* %p1
@@ -85,16 +74,6 @@
ret double* %p1
}
- define <4 x i32>* @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
- store <4 x i32> %val, <4 x i32>* %p1, align 16
- ret <4 x i32>* %p1
- }
-
- define <4 x i32>* @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
- store <4 x i32> %val, <4 x i32>* %p1, align 1
- ret <4 x i32>* %p1
- }
-
define i32* @test_load_ptr(i32** %ptr1) {
%p = load i32*, i32** %ptr1
ret i32* %p
@@ -304,62 +283,6 @@ body: |
...
---
-# ALL-LABEL: name: test_load_v4i32_noalign
-name: test_load_v4i32_noalign
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# NO_AVX512F: - { id: 1, class: vr128 }
-# AVX512ALL: - { id: 1, class: vr128x }
- - { id: 0, class: gpr }
- - { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX: %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512F: %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
- %xmm0 = COPY %1(<4 x s32>)
- RET 0, implicit %xmm0
-
-...
----
-# ALL-LABEL: name: test_load_v4i32_align
-name: test_load_v4i32_align
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# NO_AVX512F: - { id: 1, class: vr128 }
-# AVX512ALL: - { id: 1, class: vr128x }
- - { id: 0, class: gpr }
- - { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX: %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512F: %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1)
- %xmm0 = COPY %1(<4 x s32>)
- RET 0, implicit %xmm0
-
-...
----
# ALL-LABEL: name: test_store_i32
name: test_store_i32
alignment: 4
@@ -528,66 +451,6 @@ body: |
%rax = COPY %1(p0)
RET 0, implicit %rax
-...
----
-# ALL-LABEL: name: test_store_v4i32_align
-name: test_store_v4i32_align
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# NO_AVX512F: - { id: 0, class: vr128 }
-# AVX512ALL: - { id: 0, class: vr128x }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# AVX512VL: VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(<4 x s32>) = COPY %xmm0
- %1(p0) = COPY %rdi
- G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_v4i32_noalign
-name: test_store_v4i32_noalign
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# NO_AVX512F: - { id: 0, class: vr128 }
-# AVX512ALL: - { id: 0, class: vr128x }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# AVX512VL: VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(<4 x s32>) = COPY %xmm0
- %1(p0) = COPY %rdi
- G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
...
---
# ALL-LABEL: name: test_load_ptr
Added: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir?rev=303169&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir (added)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-v128.mir Tue May 16 08:37:31 2017
@@ -0,0 +1,143 @@
+# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
+# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
+
+--- |
+ define <4 x i32> @test_load_v4i32_noalign(<4 x i32>* %p1) {
+ %r = load <4 x i32>, <4 x i32>* %p1, align 1
+ ret <4 x i32> %r
+ }
+
+ define <4 x i32> @test_load_v4i32_align(<4 x i32>* %p1) {
+ %r = load <4 x i32>, <4 x i32>* %p1, align 16
+ ret <4 x i32> %r
+ }
+
+ define <4 x i32>* @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
+ store <4 x i32> %val, <4 x i32>* %p1, align 16
+ ret <4 x i32>* %p1
+ }
+
+ define <4 x i32>* @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
+ store <4 x i32> %val, <4 x i32>* %p1, align 1
+ ret <4 x i32>* %p1
+ }
+
+...
+---
+# ALL-LABEL: name: test_load_v4i32_noalign
+name: test_load_v4i32_noalign
+alignment: 4
+legalized: true
+regBankSelected: true
+registers:
+# ALL: - { id: 0, class: gr64 }
+# NO_AVX512F: - { id: 1, class: vr128 }
+# AVX512ALL: - { id: 1, class: vr128x }
+ - { id: 0, class: gpr }
+ - { id: 1, class: vecr }
+# ALL: %0 = COPY %rdi
+# SSE: %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX: %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX512F: %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
+# ALL: %xmm0 = COPY %1
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %rdi
+
+ %0(p0) = COPY %rdi
+ %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
+ %xmm0 = COPY %1(<4 x s32>)
+ RET 0, implicit %xmm0
+
+...
+---
+# ALL-LABEL: name: test_load_v4i32_align
+name: test_load_v4i32_align
+alignment: 4
+legalized: true
+regBankSelected: true
+registers:
+# ALL: - { id: 0, class: gr64 }
+# NO_AVX512F: - { id: 1, class: vr128 }
+# AVX512ALL: - { id: 1, class: vr128x }
+ - { id: 0, class: gpr }
+ - { id: 1, class: vecr }
+# ALL: %0 = COPY %rdi
+# SSE: %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX: %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX512F: %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
+# ALL: %xmm0 = COPY %1
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %rdi
+
+ %0(p0) = COPY %rdi
+ %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1)
+ %xmm0 = COPY %1(<4 x s32>)
+ RET 0, implicit %xmm0
+
+...
+---
+# ALL-LABEL: name: test_store_v4i32_align
+name: test_store_v4i32_align
+alignment: 4
+legalized: true
+regBankSelected: true
+registers:
+# NO_AVX512F: - { id: 0, class: vr128 }
+# AVX512ALL: - { id: 0, class: vr128x }
+# ALL: - { id: 1, class: gr64 }
+ - { id: 0, class: vecr }
+ - { id: 1, class: gpr }
+# ALL: %0 = COPY %xmm0
+# ALL: %1 = COPY %rdi
+# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
+# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
+# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
+# AVX512VL: VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
+# ALL: %rax = COPY %1
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %rdi, %xmm0
+
+ %0(<4 x s32>) = COPY %xmm0
+ %1(p0) = COPY %rdi
+ G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16)
+ %rax = COPY %1(p0)
+ RET 0, implicit %rax
+
+...
+---
+# ALL-LABEL: name: test_store_v4i32_noalign
+name: test_store_v4i32_noalign
+alignment: 4
+legalized: true
+regBankSelected: true
+registers:
+# NO_AVX512F: - { id: 0, class: vr128 }
+# AVX512ALL: - { id: 0, class: vr128x }
+# ALL: - { id: 1, class: gr64 }
+ - { id: 0, class: vecr }
+ - { id: 1, class: gpr }
+# ALL: %0 = COPY %xmm0
+# ALL: %1 = COPY %rdi
+# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
+# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
+# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
+# AVX512VL: VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
+# ALL: %rax = COPY %1
+body: |
+ bb.1 (%ir-block.0):
+ liveins: %rdi, %xmm0
+
+ %0(<4 x s32>) = COPY %xmm0
+ %1(p0) = COPY %rdi
+ G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1)
+ %rax = COPY %1(p0)
+ RET 0, implicit %rax
+
+...
Removed: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir?rev=303168&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop-x32.mir (removed)
@@ -1,310 +0,0 @@
-# RUN: llc -mtriple=i386-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
-
---- |
- define i8 @test_load_i8(i8* %p1) {
- %r = load i8, i8* %p1
- ret i8 %r
- }
-
- define i16 @test_load_i16(i16* %p1) {
- %r = load i16, i16* %p1
- ret i16 %r
- }
-
- define i32 @test_load_i32(i32* %p1) {
- %r = load i32, i32* %p1
- ret i32 %r
- }
-
- define i8* @test_store_i8(i8 %val, i8* %p1) {
- store i8 %val, i8* %p1
- ret i8* %p1
- }
-
- define i16* @test_store_i16(i16 %val, i16* %p1) {
- store i16 %val, i16* %p1
- ret i16* %p1
- }
-
- define i32* @test_store_i32(i32 %val, i32* %p1) {
- store i32 %val, i32* %p1
- ret i32* %p1
- }
-
- define i32* @test_load_ptr(i32** %ptr1) {
- %p = load i32*, i32** %ptr1
- ret i32* %p
- }
-
- define void @test_store_ptr(i32** %ptr1, i32* %a) {
- store i32* %a, i32** %ptr1
- ret void
- }
-
-...
----
-name: test_load_i8
-# ALL-LABEL: name: test_load_i8
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr8 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-fixedStack:
- - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-# ALL-NEXT: %2 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
-# ALL-NEXT: %al = COPY %2
-# ALL-NEXT: RET 0, implicit %al
-body: |
- bb.1 (%ir-block.0):
- %1(p0) = G_FRAME_INDEX %fixed-stack.0
- %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- %2(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
- %al = COPY %2(s8)
- RET 0, implicit %al
-
-...
----
-name: test_load_i16
-# ALL-LABEL: name: test_load_i16
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr16 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-fixedStack:
- - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-# ALL-NEXT: %2 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
-# ALL-NEXT: %ax = COPY %2
-# ALL-NEXT: RET 0, implicit %ax
-body: |
- bb.1 (%ir-block.0):
- %1(p0) = G_FRAME_INDEX %fixed-stack.0
- %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- %2(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
- %ax = COPY %2(s16)
- RET 0, implicit %ax
-
-...
----
-name: test_load_i32
-# ALL-LABEL: name: test_load_i32
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-fixedStack:
- - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-# ALL-NEXT: %2 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# ALL-NEXT: %eax = COPY %2
-# ALL-NEXT: RET 0, implicit %eax
-body: |
- bb.1 (%ir-block.0):
- %1(p0) = G_FRAME_INDEX %fixed-stack.0
- %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- %2(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
- %eax = COPY %2(s32)
- RET 0, implicit %eax
-
-...
----
-name: test_store_i8
-# ALL-LABEL: name: test_store_i8
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr8 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr32 }
-# ALL-NEXT: - { id: 3, class: gr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
-fixedStack:
- - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- - { id: 1, offset: 0, size: 1, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV8rm %2, 1, _, 0, _ :: (invariant load 1 from %fixed-stack.0, align 0)
-# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _
-# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
-# ALL-NEXT: MOV8mr %1, 1, _, 0, _, %0 :: (store 1 into %ir.p1)
-# ALL-NEXT: %eax = COPY %1
-# ALL-NEXT: RET 0, implicit %eax
-body: |
- bb.1 (%ir-block.0):
- %2(p0) = G_FRAME_INDEX %fixed-stack.1
- %0(s8) = G_LOAD %2(p0) :: (invariant load 1 from %fixed-stack.1, align 0)
- %3(p0) = G_FRAME_INDEX %fixed-stack.0
- %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- G_STORE %0(s8), %1(p0) :: (store 1 into %ir.p1)
- %eax = COPY %1(p0)
- RET 0, implicit %eax
-
-...
----
-name: test_store_i16
-# ALL-LABEL: name: test_store_i16
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr16 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr32 }
-# ALL-NEXT: - { id: 3, class: gr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
-fixedStack:
- - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- - { id: 1, offset: 0, size: 2, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV16rm %2, 1, _, 0, _ :: (invariant load 2 from %fixed-stack.0, align 0)
-# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _
-# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
-# ALL-NEXT: MOV16mr %1, 1, _, 0, _, %0 :: (store 2 into %ir.p1)
-# ALL-NEXT: %eax = COPY %1
-# ALL-NEXT: RET 0, implicit %eax
-body: |
- bb.1 (%ir-block.0):
- %2(p0) = G_FRAME_INDEX %fixed-stack.1
- %0(s16) = G_LOAD %2(p0) :: (invariant load 2 from %fixed-stack.1, align 0)
- %3(p0) = G_FRAME_INDEX %fixed-stack.0
- %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- G_STORE %0(s16), %1(p0) :: (store 2 into %ir.p1)
- %eax = COPY %1(p0)
- RET 0, implicit %eax
-
-...
----
-name: test_store_i32
-# ALL-LABEL: name: test_store_i32
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr32 }
-# ALL-NEXT: - { id: 3, class: gr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
-fixedStack:
- - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV32rm %2, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _
-# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
-# ALL-NEXT: MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
-# ALL-NEXT: %eax = COPY %1
-# ALL-NEXT: RET 0, implicit %eax
-body: |
- bb.1 (%ir-block.0):
- %2(p0) = G_FRAME_INDEX %fixed-stack.1
- %0(s32) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
- %3(p0) = G_FRAME_INDEX %fixed-stack.0
- %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
- %eax = COPY %1(p0)
- RET 0, implicit %eax
-
-...
----
-name: test_load_ptr
-# ALL-LABEL: name: test_load_ptr
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-fixedStack:
- - { id: 0, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %1 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV32rm %1, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-# ALL-NEXT: %2 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.ptr1)
-# ALL-NEXT: %eax = COPY %2
-# ALL-NEXT: RET 0, implicit %eax
-body: |
- bb.1 (%ir-block.0):
- %1(p0) = G_FRAME_INDEX %fixed-stack.0
- %0(p0) = G_LOAD %1(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- %2(p0) = G_LOAD %0(p0) :: (load 4 from %ir.ptr1)
- %eax = COPY %2(p0)
- RET 0, implicit %eax
-
-...
----
-name: test_store_ptr
-# ALL-LABEL: name: test_store_ptr
-alignment: 4
-legalized: true
-regBankSelected: true
-# ALL: registers:
-# ALL-NEXT: - { id: 0, class: gr32 }
-# ALL-NEXT: - { id: 1, class: gr32 }
-# ALL-NEXT: - { id: 2, class: gr32 }
-# ALL-NEXT: - { id: 3, class: gr32 }
-registers:
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
- - { id: 3, class: gpr }
-fixedStack:
- - { id: 0, offset: 4, size: 4, alignment: 4, isImmutable: true, isAliased: false }
- - { id: 1, offset: 0, size: 4, alignment: 16, isImmutable: true, isAliased: false }
-# ALL: %2 = LEA32r %fixed-stack.0, 1, _, 0, _
-# ALL-NEXT: %0 = MOV32rm %2, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.0, align 0)
-# ALL-NEXT: %3 = LEA32r %fixed-stack.1, 1, _, 0, _
-# ALL-NEXT: %1 = MOV32rm %3, 1, _, 0, _ :: (invariant load 4 from %fixed-stack.1, align 0)
-# ALL-NEXT: MOV32mr %0, 1, _, 0, _, %1 :: (store 4 into %ir.ptr1)
-# ALL-NEXT: RET 0
-body: |
- bb.1 (%ir-block.0):
- %2(p0) = G_FRAME_INDEX %fixed-stack.1
- %0(p0) = G_LOAD %2(p0) :: (invariant load 4 from %fixed-stack.1, align 0)
- %3(p0) = G_FRAME_INDEX %fixed-stack.0
- %1(p0) = G_LOAD %3(p0) :: (invariant load 4 from %fixed-stack.0, align 0)
- G_STORE %1(p0), %0(p0) :: (store 4 into %ir.ptr1)
- RET 0
-
-...
Removed: llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir?rev=303168&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir (original)
+++ llvm/trunk/test/CodeGen/X86/GlobalISel/select-memop.mir (removed)
@@ -1,637 +0,0 @@
-# RUN: llc -mtriple=x86_64-linux-gnu -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
-# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
-
---- |
- define i8 @test_load_i8(i8* %p1) {
- %r = load i8, i8* %p1
- ret i8 %r
- }
-
- define i16 @test_load_i16(i16* %p1) {
- %r = load i16, i16* %p1
- ret i16 %r
- }
-
- define i32 @test_load_i32(i32* %p1) {
- %r = load i32, i32* %p1
- ret i32 %r
- }
-
- define i64 @test_load_i64(i64* %p1) {
- %r = load i64, i64* %p1
- ret i64 %r
- }
-
- define float @test_load_float(float* %p1) {
- %r = load float, float* %p1
- ret float %r
- }
-
- define float @test_load_float_vecreg(float* %p1) {
- %r = load float, float* %p1
- ret float %r
- }
-
-
- define double @test_load_double(double* %p1) {
- %r = load double, double* %p1
- ret double %r
- }
-
- define double @test_load_double_vecreg(double* %p1) {
- %r = load double, double* %p1
- ret double %r
- }
-
- define <4 x i32> @test_load_v4i32_noalign(<4 x i32>* %p1) {
- %r = load <4 x i32>, <4 x i32>* %p1, align 1
- ret <4 x i32> %r
- }
-
- define <4 x i32> @test_load_v4i32_align(<4 x i32>* %p1) {
- %r = load <4 x i32>, <4 x i32>* %p1, align 16
- ret <4 x i32> %r
- }
-
- define i32* @test_store_i32(i32 %val, i32* %p1) {
- store i32 %val, i32* %p1
- ret i32* %p1
- }
-
- define i64* @test_store_i64(i64 %val, i64* %p1) {
- store i64 %val, i64* %p1
- ret i64* %p1
- }
-
- define float* @test_store_float(float %val, float* %p1) {
- store float %val, float* %p1
- ret float* %p1
- }
-
- define float* @test_store_float_vec(float %val, float* %p1) {
- store float %val, float* %p1
- ret float* %p1
- }
-
- define double* @test_store_double(double %val, double* %p1) {
- store double %val, double* %p1
- ret double* %p1
- }
-
- define double* @test_store_double_vec(double %val, double* %p1) {
- store double %val, double* %p1
- ret double* %p1
- }
-
- define <4 x i32>* @test_store_v4i32_align(<4 x i32> %val, <4 x i32>* %p1) {
- store <4 x i32> %val, <4 x i32>* %p1, align 16
- ret <4 x i32>* %p1
- }
-
- define <4 x i32>* @test_store_v4i32_noalign(<4 x i32> %val, <4 x i32>* %p1) {
- store <4 x i32> %val, <4 x i32>* %p1, align 1
- ret <4 x i32>* %p1
- }
-
- define i32* @test_load_ptr(i32** %ptr1) {
- %p = load i32*, i32** %ptr1
- ret i32* %p
- }
-
- define void @test_store_ptr(i32** %ptr1, i32* %a) {
- store i32* %a, i32** %ptr1
- ret void
- }
-...
----
-# ALL-LABEL: name: test_load_i8
-name: test_load_i8
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr8 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV8rm %0, 1, _, 0, _ :: (load 1 from %ir.p1)
-# ALL: %al = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s8) = G_LOAD %0(p0) :: (load 1 from %ir.p1)
- %al = COPY %1(s8)
- RET 0, implicit %al
-
-...
----
-# ALL-LABEL: name: test_load_i16
-name: test_load_i16
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr16 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV16rm %0, 1, _, 0, _ :: (load 2 from %ir.p1)
-# ALL: %ax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s16) = G_LOAD %0(p0) :: (load 2 from %ir.p1)
- %ax = COPY %1(s16)
- RET 0, implicit %ax
-
-...
----
-# ALL-LABEL: name: test_load_i32
-name: test_load_i32
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr32 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# ALL: %eax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
- %eax = COPY %1(s32)
- RET 0, implicit %eax
-
-...
----
-# ALL-LABEL: name: test_load_i64
-name: test_load_i64
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
- %rax = COPY %1(s64)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_load_float
-name: test_load_float
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr32 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV32rm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
- %xmm0 = COPY %1(s32)
- RET 0, implicit %xmm0
-
-...
----
-# ALL-LABEL: name: test_load_float_vecreg
-name: test_load_float_vecreg
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# NO_AVX512F: - { id: 1, class: fr32 }
-# AVX512ALL: - { id: 1, class: fr32x }
- - { id: 0, class: gpr }
- - { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# AVX: %1 = VMOVSSrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# AVX512ALL: %1 = VMOVSSZrm %0, 1, _, 0, _ :: (load 4 from %ir.p1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s32) = G_LOAD %0(p0) :: (load 4 from %ir.p1)
- %xmm0 = COPY %1(s32)
- RET 0, implicit %xmm0
-
-...
----
-# ALL-LABEL: name: test_load_double
-name: test_load_double
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
- %xmm0 = COPY %1(s64)
- RET 0, implicit %xmm0
-
-...
----
-# ALL-LABEL: name: test_load_double_vecreg
-name: test_load_double_vecreg
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# NO_AVX512F: - { id: 1, class: fr64 }
-# AVX512ALL: - { id: 1, class: fr64x }
- - { id: 0, class: gpr }
- - { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# AVX: %1 = VMOVSDrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# AVX512ALL: %1 = VMOVSDZrm %0, 1, _, 0, _ :: (load 8 from %ir.p1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(s64) = G_LOAD %0(p0) :: (load 8 from %ir.p1)
- %xmm0 = COPY %1(s64)
- RET 0, implicit %xmm0
-
-...
----
-# ALL-LABEL: name: test_load_v4i32_noalign
-name: test_load_v4i32_noalign
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# NO_AVX512F: - { id: 1, class: vr128 }
-# AVX512ALL: - { id: 1, class: vr128x }
- - { id: 0, class: gpr }
- - { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX: %1 = VMOVUPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512F: %1 = VMOVUPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# AVX512VL: %1 = VMOVUPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1, align 1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1, align 1)
- %xmm0 = COPY %1(<4 x s32>)
- RET 0, implicit %xmm0
-
-...
----
-# ALL-LABEL: name: test_load_v4i32_align
-name: test_load_v4i32_align
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# NO_AVX512F: - { id: 1, class: vr128 }
-# AVX512ALL: - { id: 1, class: vr128x }
- - { id: 0, class: gpr }
- - { id: 1, class: vecr }
-# ALL: %0 = COPY %rdi
-# SSE: %1 = MOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX: %1 = VMOVAPSrm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512F: %1 = VMOVAPSZ128rm_NOVLX %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# AVX512VL: %1 = VMOVAPSZ128rm %0, 1, _, 0, _ :: (load 16 from %ir.p1)
-# ALL: %xmm0 = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(<4 x s32>) = G_LOAD %0(p0) :: (load 16 from %ir.p1)
- %xmm0 = COPY %1(<4 x s32>)
- RET 0, implicit %xmm0
-
-...
----
-# ALL-LABEL: name: test_store_i32
-name: test_store_i32
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr32 }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %edi
-# ALL: %1 = COPY %rsi
-# ALL: MOV32mr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %edi, %rsi
-
- %0(s32) = COPY %edi
- %1(p0) = COPY %rsi
- G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_i64
-name: test_store_i64
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %rdi
-# ALL: %1 = COPY %rsi
-# ALL: MOV64mr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %rsi
-
- %0(s64) = COPY %rdi
- %1(p0) = COPY %rsi
- G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_float
-name: test_store_float
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: fr32x }
-# ALL: - { id: 1, class: gr64 }
-# ALL: - { id: 2, class: gr32 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# ALL: %2 = COPY %0
-# ALL: MOV32mr %1, 1, _, 0, _, %2 :: (store 4 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(s32) = COPY %xmm0
- %1(p0) = COPY %rdi
- %2(s32) = COPY %0(s32)
- G_STORE %2(s32), %1(p0) :: (store 4 into %ir.p1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_float_vec
-name: test_store_float_vec
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# NO_AVX512F: - { id: 0, class: fr32 }
-# AVX512ALL: - { id: 0, class: fr32x }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# SSE: MOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
-# AVX: VMOVSSmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
-# AVX512ALL: VMOVSSZmr %1, 1, _, 0, _, %0 :: (store 4 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(s32) = COPY %xmm0
- %1(p0) = COPY %rdi
- G_STORE %0(s32), %1(p0) :: (store 4 into %ir.p1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_double
-name: test_store_double
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# ALL: - { id: 0, class: fr64x }
-# ALL: - { id: 1, class: gr64 }
-# ALL: - { id: 2, class: gr64 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
- - { id: 2, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# ALL: %2 = COPY %0
-# ALL: MOV64mr %1, 1, _, 0, _, %2 :: (store 8 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(s64) = COPY %xmm0
- %1(p0) = COPY %rdi
- %2(s64) = COPY %0(s64)
- G_STORE %2(s64), %1(p0) :: (store 8 into %ir.p1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_double_vec
-name: test_store_double_vec
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# NO_AVX512F: - { id: 0, class: fr64 }
-# AVX512ALL: - { id: 0, class: fr64x }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# SSE: MOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
-# AVX: VMOVSDmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
-# AVX512ALL: VMOVSDZmr %1, 1, _, 0, _, %0 :: (store 8 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(s64) = COPY %xmm0
- %1(p0) = COPY %rdi
- G_STORE %0(s64), %1(p0) :: (store 8 into %ir.p1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_v4i32_align
-name: test_store_v4i32_align
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# NO_AVX512F: - { id: 0, class: vr128 }
-# AVX512ALL: - { id: 0, class: vr128x }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# SSE: MOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# AVX: VMOVAPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# AVX512F: VMOVAPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# AVX512VL: VMOVAPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(<4 x s32>) = COPY %xmm0
- %1(p0) = COPY %rdi
- G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 16)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_v4i32_noalign
-name: test_store_v4i32_noalign
-alignment: 4
-legalized: true
-regBankSelected: true
-registers:
-# NO_AVX512F: - { id: 0, class: vr128 }
-# AVX512ALL: - { id: 0, class: vr128x }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: vecr }
- - { id: 1, class: gpr }
-# ALL: %0 = COPY %xmm0
-# ALL: %1 = COPY %rdi
-# SSE: MOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# AVX: VMOVUPSmr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# AVX512F: VMOVUPSZ128mr_NOVLX %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# AVX512VL: VMOVUPSZ128mr %1, 1, _, 0, _, %0 :: (store 16 into %ir.p1, align 1)
-# ALL: %rax = COPY %1
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %xmm0
-
- %0(<4 x s32>) = COPY %xmm0
- %1(p0) = COPY %rdi
- G_STORE %0(<4 x s32>), %1(p0) :: (store 16 into %ir.p1, align 1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_load_ptr
-name: test_load_ptr
-alignment: 4
-legalized: true
-regBankSelected: true
-selected: false
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: %1 = MOV64rm %0, 1, _, 0, _ :: (load 8 from %ir.ptr1)
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi
-
- %0(p0) = COPY %rdi
- %1(p0) = G_LOAD %0(p0) :: (load 8 from %ir.ptr1)
- %rax = COPY %1(p0)
- RET 0, implicit %rax
-
-...
----
-# ALL-LABEL: name: test_store_ptr
-name: test_store_ptr
-alignment: 4
-legalized: true
-regBankSelected: true
-selected: false
-registers:
-# ALL: - { id: 0, class: gr64 }
-# ALL: - { id: 1, class: gr64 }
- - { id: 0, class: gpr }
- - { id: 1, class: gpr }
-# ALL: MOV64mr %0, 1, _, 0, _, %1 :: (store 8 into %ir.ptr1)
-body: |
- bb.1 (%ir-block.0):
- liveins: %rdi, %rsi
-
- %0(p0) = COPY %rdi
- %1(p0) = COPY %rsi
- G_STORE %1(p0), %0(p0) :: (store 8 into %ir.ptr1)
- RET 0
-
-...
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