[PATCH] D33099: AMD Jaguar scheduler doesn't correctly model 256-bit AVX instructions

[Andrew V. Tischenko via Phabricator via llvm-commits]

avt77 updated this revision to Diff 99105.
avt77 added a comment.

I slightly changed the algorithm of throughput calculation: if the instr sched model does not have cycles for the given instruction but it's valid then throughput is equal to lattency.


https://reviews.llvm.org/D33099

Files:
  include/llvm/CodeGen/TargetSchedule.h
  lib/CodeGen/TargetSchedule.cpp
  lib/Target/X86/X86ScheduleBtVer2.td
  test/CodeGen/X86/avx-schedule.ll
  test/CodeGen/X86/recip-fastmath.ll
  test/CodeGen/X86/recip-fastmath2.ll
  test/CodeGen/X86/slow-unaligned-mem.ll
  test/CodeGen/X86/sse-schedule.ll
  test/CodeGen/X86/sse2-schedule.ll

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