[PATCH] D33196: [AArch64] Explicitly enable FeatureFuseLiterals on Cortex-A72 (NFC).

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a comment.

Hi Silviu,
yes the plan is to include FeatureFuseAES for A72 as well, I'm going to commit a patch soon that adds FeatureFuseAES for Cortex-A72 and I'll also put up a patch for review that makes instruction fusion slightly more aggressive on AArch64.

I didn't plan to do anything with respect to PostRA, but I could benchmark the difference with and without PostRA.

Cheers


https://reviews.llvm.org/D33196