[PATCH] D33186: [InstCombine] Canonicalize clamp of float types to minmax in fast mode.

Andrei Elovikov via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon May 15 06:16:34 PDT 2017


a.elovikov added a comment.

In https://reviews.llvm.org/D33186#754827, @jmolloy wrote:

> Right; that's X86's strange not-a-maxnum-not-a-maxnan behaviour where it just selects the zeroth operand.
>
> You should be able to select that for either of FMAXNAN or FMAXNUM though when the "nnan" flag is set on the instruction, which should be the case in fast-math mode?


Yes, but they're not selected at all in `SelectionDAGBuilder::visitSelect` because `ISD::FMINNAN/FMINNUM` are not `isOperationLegalOrCustom` for X86 target.
And stating that they are would be incorrect. So the only way to get X86::FMIN/FMAX would be to fix `combineSelect` in `X86ISelLowering.cpp` in the same way that I've done for IR. I believe that such manipulation is better be done on IR than on `SDNode`s


https://reviews.llvm.org/D33186





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