[llvm] r302942 - [NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Fri May 12 14:56:43 2017
New Revision: 302942

URL: http://llvm.org/viewvc/llvm-project?rev=302942&view=rev
Log:
[NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)

This fixes 47 of the 75 NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146.

Differential Revision: https://reviews.llvm.org/D33147

Modified:
    llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
    llvm/trunk/test/CodeGen/NVPTX/ctlz.ll
    llvm/trunk/test/CodeGen/NVPTX/ctpop.ll
    llvm/trunk/test/CodeGen/NVPTX/cttz.ll

Modified: llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp?rev=302942&r1=302941&r2=302942&view=diff
==============================================================================
--- llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/NVPTX/NVPTXISelLowering.cpp Fri May 12 14:56:43 2017
@@ -2578,7 +2578,9 @@ NVPTXTargetLowering::LowerReturn(SDValue
       EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
       Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
                                       StoreOperands, TheStoreType,
-                                      MachinePointerInfo(), 1);
+                                      MachinePointerInfo(), /* Align */ 1,
+                                      /* Volatile */ false, /* ReadMem */ false,
+                                      /* WriteMem */ true, /* Size */ 0);
       // Cleanup vector state.
       StoreOperands.clear();
     }

Modified: llvm/trunk/test/CodeGen/NVPTX/ctlz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/ctlz.ll?rev=302942&r1=302941&r2=302942&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/ctlz.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/ctlz.ll Fri May 12 14:56:43 2017
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 

Modified: llvm/trunk/test/CodeGen/NVPTX/ctpop.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/ctpop.ll?rev=302942&r1=302941&r2=302942&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/ctpop.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/ctpop.ll Fri May 12 14:56:43 2017
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 

Modified: llvm/trunk/test/CodeGen/NVPTX/cttz.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/NVPTX/cttz.ll?rev=302942&r1=302941&r2=302942&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/NVPTX/cttz.ll (original)
+++ llvm/trunk/test/CodeGen/NVPTX/cttz.ll Fri May 12 14:56:43 2017
@@ -1,5 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
-
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"