[PATCH] D32763: [PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.

[Kit Barton via Phabricator via llvm-commits]

kbarton added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/atomic-2.ll:114
+; CHECK: bne-
+; CHECK: isync
   ret i64 %tmp
----------------
timshen wrote:
> kbarton wrote:
> > Please add CHECK-NEXT for the bne- and isync instructions. We want to ensure the cmp, bc, isync instructions stay together. 
> I'm not sure about that.
> 
> LLVM post-RA scheduler may stick instructions in between the cmp, bc, isync sequence, but the dependencies introduced by cmp and bc are perfectly preserved.
OK, that's fair. I've verified with the hardware designers that this sequence can have unrelated instructions interleaved.
However, we also want to check that any operations we are trying to order using the sync are not moved across this sequence. Can you add a use of VAL to the test and a check to  ensure it doesn't get moved up past the isync?


https://reviews.llvm.org/D32763