[PATCH] D33147: [NVPTX] Don't flag StoreRetVal memory chain operands as ReadMem (PR32146)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
Herald added a subscriber: jholewinski.

NVPTXTargetLowering::LowerReturn was trusting the default argument values.

This fixes 47 of the 75 NVPTX '-verify-machineinstrs with EXPENSIVE_CHECKS' errors in PR32146.

I've added -verify-machineinstrs to a few of the test files, I can be more thorough if you think it useful.


Repository:
  rL LLVM

https://reviews.llvm.org/D33147

Files:
  lib/Target/NVPTX/NVPTXISelLowering.cpp
  test/CodeGen/NVPTX/ctlz.ll
  test/CodeGen/NVPTX/ctpop.ll
  test/CodeGen/NVPTX/cttz.ll


Index: test/CodeGen/NVPTX/cttz.ll
===================================================================
--- test/CodeGen/NVPTX/cttz.ll
+++ test/CodeGen/NVPTX/cttz.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
Index: test/CodeGen/NVPTX/ctpop.ll
===================================================================
--- test/CodeGen/NVPTX/ctpop.ll
+++ test/CodeGen/NVPTX/ctpop.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 
Index: test/CodeGen/NVPTX/ctlz.ll
===================================================================
--- test/CodeGen/NVPTX/ctlz.ll
+++ test/CodeGen/NVPTX/ctlz.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -march=nvptx -mcpu=sm_20 | FileCheck %s
+; RUN: llc < %s -march=nvptx -mcpu=sm_20 -verify-machineinstrs | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-n16:32:64"
 
Index: lib/Target/NVPTX/NVPTXISelLowering.cpp
===================================================================
--- lib/Target/NVPTX/NVPTXISelLowering.cpp
+++ lib/Target/NVPTX/NVPTXISelLowering.cpp
@@ -2578,7 +2578,9 @@
       EVT TheStoreType = ExtendIntegerRetVal ? MVT::i32 : VTs[i];
       Chain = DAG.getMemIntrinsicNode(Op, dl, DAG.getVTList(MVT::Other),
                                       StoreOperands, TheStoreType,
-                                      MachinePointerInfo(), 1);
+                                      MachinePointerInfo(), /* Align */ 1,
+                                      /* Volatile */ false, /* ReadMem */ false,
+                                      /* WriteMem */ true, /* Size */ 0);
       // Cleanup vector state.
       StoreOperands.clear();
     }


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