[PATCH] D32869: [globalisel][tablegen] Require that all registers between instructions of a match are virtual.

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet accepted this revision.
qcolombet added a comment.
This revision is now accepted and ready to land.

Thanks for the clarification, now I get it :).

The proposed approach sounds good. I was think that this will prevent us form having patterns with target specific opcodes (and thus implicit-def/use) but we can revisit if/when we get to that.


https://reviews.llvm.org/D32869