[PATCH] D32869: [globalisel][tablegen] Require that all registers between instructions of a match are virtual.

[Quentin Colombet via Phabricator via llvm-commits]

qcolombet added a comment.

Hi Daniel,

We are talking pass each other :).

I think I miss the use case you want to solve.

On my side, I thought you wanted to fallback on cases where we have a physical register use or def like in ADJUSTSTACKxxx.

  let Defs = [SP], Uses = [SP], [...] // <-- I am talking about that
  [...]
  def ADJCALLSTACKDOWN : [...]
  [...]

Whereas I was saying we want to handle such case like this:
SP = vregIn
SP = ADJCALL SP
vregOut = SP

instead of falling back, given it will happen.

Cheers,
-Quentin


https://reviews.llvm.org/D32869