[llvm] r302782 - [ARM][GlobalISel] Legalize narrow scalar ops by widening
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Thu May 11 02:45:58 PDT 2017
Author: rovka
Date: Thu May 11 04:45:57 2017
New Revision: 302782
URL: http://llvm.org/viewvc/llvm-project?rev=302782&view=rev
Log:
[ARM][GlobalISel] Legalize narrow scalar ops by widening
This is the same as r292827 for AArch64: we widen 8- and 16-bit ADD, SUB
and MUL to 32 bits since we only have TableGen patterns for 32 bits.
See the commit message for r292827 for more details.
At this point we could just remove some of the tests for regbankselect
and instruction-select, since we're not going to see any narrow
operations at those levels anymore. Instead I decided to update them
with G_ANYEXT/G_TRUNC operations, so we can validate the full sequences
generated by the legalizer.
Modified:
llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp?rev=302782&r1=302781&r2=302782&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMLegalizerInfo.cpp Thu May 11 04:45:57 2017
@@ -45,9 +45,11 @@ ARMLegalizerInfo::ARMLegalizerInfo(const
setAction({Op, 1, p0}, Legal);
}
- for (unsigned Op : {G_ADD, G_SUB, G_MUL})
- for (auto Ty : {s1, s8, s16, s32})
- setAction({Op, Ty}, Legal);
+ for (unsigned Op : {G_ADD, G_SUB, G_MUL}) {
+ for (auto Ty : {s1, s8, s16})
+ setAction({Op, Ty}, WidenScalar);
+ setAction({Op, s32}, Legal);
+ }
for (unsigned Op : {G_SDIV, G_UDIV}) {
for (auto Ty : {s8, s16})
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=302782&r1=302781&r2=302782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Thu May 11 04:45:57 2017
@@ -241,9 +241,15 @@ registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
+# CHECK-DAG: id: 3, class: gpr
+# CHECK-DAG: id: 4, class: gpr
+# CHECK-DAG: id: 5, class: gpr
body: |
bb.0:
liveins: %r0, %r1
@@ -254,11 +260,20 @@ body: |
%1(s8) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s8) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+ %2(s32) = G_ANYEXT %0(s8)
+ ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
- %r0 = COPY %2(s8)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ %3(s32) = G_ANYEXT %1(s8)
+ ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
+
+ %4(s32) = G_ADD %2, %3
+ ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
+
+ %5(s8) = G_TRUNC %4(s32)
+ ; CHECK: [[VREGSUMTR:%[0-9]+]] = COPY [[VREGSUM]]
+
+ %r0 = COPY %5(s8)
+ ; CHECK: %r0 = COPY [[VREGSUMTR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
@@ -274,9 +289,15 @@ registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
+# CHECK-DAG: id: 3, class: gpr
+# CHECK-DAG: id: 4, class: gpr
+# CHECK-DAG: id: 5, class: gpr
body: |
bb.0:
liveins: %r0, %r1
@@ -287,11 +308,20 @@ body: |
%1(s16) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s16) = G_ADD %0, %1
- ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGX]], [[VREGY]], 14, _, _
+ %2(s32) = G_ANYEXT %0(s16)
+ ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
- %r0 = COPY %2(s16)
- ; CHECK: %r0 = COPY [[VREGSUM]]
+ %3(s32) = G_ANYEXT %1(s16)
+ ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
+
+ %4(s32) = G_ADD %2, %3
+ ; CHECK: [[VREGSUM:%[0-9]+]] = ADDrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
+
+ %5(s16) = G_TRUNC %4(s32)
+ ; CHECK: [[VREGSUMTR:%[0-9]+]] = COPY [[VREGSUM]]
+
+ %r0 = COPY %5(s16)
+ ; CHECK: %r0 = COPY [[VREGSUMTR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
@@ -406,9 +436,15 @@ registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
+# CHECK-DAG: id: 3, class: gpr
+# CHECK-DAG: id: 4, class: gpr
+# CHECK-DAG: id: 5, class: gpr
body: |
bb.0:
liveins: %r0, %r1
@@ -419,11 +455,20 @@ body: |
%1(s8) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s8) = G_SUB %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGX]], [[VREGY]], 14, _, _
+ %2(s32) = G_ANYEXT %0(s8)
+ ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
- %r0 = COPY %2(s8)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ %3(s32) = G_ANYEXT %1(s8)
+ ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
+
+ %4(s32) = G_SUB %2, %3
+ ; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
+
+ %5(s8) = G_TRUNC %4(s32)
+ ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
+
+ %r0 = COPY %5(s8)
+ ; CHECK: %r0 = COPY [[VREGRESTR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
@@ -439,9 +484,15 @@ registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
# CHECK-DAG: id: 0, class: gpr
# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gpr
+# CHECK-DAG: id: 3, class: gpr
+# CHECK-DAG: id: 4, class: gpr
+# CHECK-DAG: id: 5, class: gpr
body: |
bb.0:
liveins: %r0, %r1
@@ -452,11 +503,20 @@ body: |
%1(s16) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s16) = G_SUB %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGX]], [[VREGY]], 14, _, _
+ %2(s32) = G_ANYEXT %0(s16)
+ ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
- %r0 = COPY %2(s16)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ %3(s32) = G_ANYEXT %1(s16)
+ ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
+
+ %4(s32) = G_SUB %2, %3
+ ; CHECK: [[VREGRES:%[0-9]+]] = SUBrr [[VREGXEXT]], [[VREGYEXT]], 14, _, _
+
+ %5(s16) = G_TRUNC %4(s32)
+ ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
+
+ %r0 = COPY %5(s16)
+ ; CHECK: %r0 = COPY [[VREGRESTR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
@@ -505,9 +565,15 @@ registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
-# CHECK-DAG: id: 0, class: gprnopc
-# CHECK-DAG: id: 1, class: gprnopc
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+# CHECK-DAG: id: 0, class: gpr
+# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gprnopc
+# CHECK-DAG: id: 3, class: gprnopc
+# CHECK-DAG: id: 4, class: gprnopc
+# CHECK-DAG: id: 5, class: gpr
body: |
bb.0:
liveins: %r0, %r1
@@ -518,11 +584,20 @@ body: |
%1(s8) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s8) = G_MUL %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGX]], [[VREGY]], 14, _, _
+ %2(s32) = G_ANYEXT %0(s8)
+ ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
- %r0 = COPY %2(s8)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ %3(s32) = G_ANYEXT %1(s8)
+ ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
+
+ %4(s32) = G_MUL %2, %3
+ ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGXEXT]], [[VREGYEXT]], 14, _, _
+
+ %5(s8) = G_TRUNC %4(s32)
+ ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
+
+ %r0 = COPY %5(s8)
+ ; CHECK: %r0 = COPY [[VREGRESTR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
@@ -538,9 +613,15 @@ registers:
- { id: 0, class: gprb }
- { id: 1, class: gprb }
- { id: 2, class: gprb }
-# CHECK-DAG: id: 0, class: gprnopc
-# CHECK-DAG: id: 1, class: gprnopc
+ - { id: 3, class: gprb }
+ - { id: 4, class: gprb }
+ - { id: 5, class: gprb }
+# CHECK-DAG: id: 0, class: gpr
+# CHECK-DAG: id: 1, class: gpr
# CHECK-DAG: id: 2, class: gprnopc
+# CHECK-DAG: id: 3, class: gprnopc
+# CHECK-DAG: id: 4, class: gprnopc
+# CHECK-DAG: id: 5, class: gpr
body: |
bb.0:
liveins: %r0, %r1
@@ -551,11 +632,20 @@ body: |
%1(s16) = COPY %r1
; CHECK: [[VREGY:%[0-9]+]] = COPY %r1
- %2(s16) = G_MUL %0, %1
- ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGX]], [[VREGY]], 14, _, _
+ %2(s32) = G_ANYEXT %0(s16)
+ ; CHECK: [[VREGXEXT:%[0-9]+]] = COPY [[VREGX]]
- %r0 = COPY %2(s16)
- ; CHECK: %r0 = COPY [[VREGRES]]
+ %3(s32) = G_ANYEXT %1(s16)
+ ; CHECK: [[VREGYEXT:%[0-9]+]] = COPY [[VREGY]]
+
+ %4(s32) = G_MUL %2, %3
+ ; CHECK: [[VREGRES:%[0-9]+]] = MUL [[VREGXEXT]], [[VREGYEXT]], 14, _, _
+
+ %5(s16) = G_TRUNC %4(s32)
+ ; CHECK: [[VREGRESTR:%[0-9]+]] = COPY [[VREGRES]]
+
+ %r0 = COPY %5(s16)
+ ; CHECK: %r0 = COPY [[VREGRESTR]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir?rev=302782&r1=302781&r2=302782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-legalizer.mir Thu May 11 04:45:57 2017
@@ -91,8 +91,9 @@ body: |
%0(s8) = COPY %r0
%1(s8) = COPY %r1
%2(s8) = G_ADD %0, %1
- ; G_ADD with s8 is legal, so we should find it unchanged in the output
- ; CHECK: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
+ ; G_ADD with s8 should widen
+ ; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
+ ; CHECK-NOT: {{%[0-9]+}}(s8) = G_ADD {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s8)
BX_RET 14, _, implicit %r0
...
@@ -115,8 +116,9 @@ body: |
%0(s16) = COPY %r0
%1(s16) = COPY %r1
%2(s16) = G_ADD %0, %1
- ; G_ADD with s16 is legal, so we should find it unchanged in the output
- ; CHECK: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
+ ; G_ADD with s16 should widen
+ ; CHECK: {{%[0-9]+}}(s32) = G_ADD {{%[0-9]+, %[0-9]+}}
+ ; CHECK-NOT: {{%[0-9]+}}(s16) = G_ADD {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s16)
BX_RET 14, _, implicit %r0
@@ -165,8 +167,9 @@ body: |
%0(s8) = COPY %r0
%1(s8) = COPY %r1
%2(s8) = G_SUB %0, %1
- ; G_SUB with s8 is legal, so we should find it unchanged in the output
- ; CHECK: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
+ ; G_SUB with s8 should widen
+ ; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
+ ; CHECK-NOT: {{%[0-9]+}}(s8) = G_SUB {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s8)
BX_RET 14, _, implicit %r0
...
@@ -189,8 +192,9 @@ body: |
%0(s16) = COPY %r0
%1(s16) = COPY %r1
%2(s16) = G_SUB %0, %1
- ; G_SUB with s16 is legal, so we should find it unchanged in the output
- ; CHECK: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
+ ; G_SUB with s16 should widen
+ ; CHECK: {{%[0-9]+}}(s32) = G_SUB {{%[0-9]+, %[0-9]+}}
+ ; CHECK-NOT: {{%[0-9]+}}(s16) = G_SUB {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s16)
BX_RET 14, _, implicit %r0
@@ -239,8 +243,9 @@ body: |
%0(s8) = COPY %r0
%1(s8) = COPY %r1
%2(s8) = G_MUL %0, %1
- ; G_MUL with s8 is legal, so we should find it unchanged in the output
- ; CHECK: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
+ ; G_MUL with s8 should widen
+ ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
+ ; CHECK-NOT: {{%[0-9]+}}(s8) = G_MUL {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s8)
BX_RET 14, _, implicit %r0
...
@@ -263,8 +268,9 @@ body: |
%0(s16) = COPY %r0
%1(s16) = COPY %r1
%2(s16) = G_MUL %0, %1
- ; G_MUL with s16 is legal, so we should find it unchanged in the output
- ; CHECK: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
+ ; G_MUL with s16 should widen
+ ; CHECK: {{%[0-9]+}}(s32) = G_MUL {{%[0-9]+, %[0-9]+}}
+ ; CHECK-NOT: {{%[0-9]+}}(s16) = G_MUL {{%[0-9]+, %[0-9]+}}
%r0 = COPY %2(s16)
BX_RET 14, _, implicit %r0
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=302782&r1=302781&r2=302782&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Thu May 11 04:45:57 2017
@@ -74,19 +74,28 @@ selected: false
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
%1(s16) = COPY %r1
- %2(s16) = G_ADD %0, %1
- %r0 = COPY %2(s16)
+ %2(s32) = G_ANYEXT %0(s16)
+ %3(s32) = G_ANYEXT %1(s16)
+ %4(s32) = G_ADD %2, %3
+ %5(s16) = G_TRUNC %4(s32)
+ %r0 = COPY %5(s16)
BX_RET 14, _, implicit %r0
...
@@ -100,19 +109,28 @@ selected: false
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
%1(s8) = COPY %r1
- %2(s8) = G_ADD %0, %1
- %r0 = COPY %2(s8)
+ %2(s32) = G_ANYEXT %0(s8)
+ %3(s32) = G_ANYEXT %1(s8)
+ %4(s32) = G_ADD %2, %3
+ %5(s8) = G_TRUNC %4(s32)
+ %r0 = COPY %5(s8)
BX_RET 14, _, implicit %r0
...
@@ -126,19 +144,28 @@ selected: false
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s1) = COPY %r0
%1(s1) = COPY %r1
- %2(s1) = G_ADD %0, %1
- %r0 = COPY %2(s1)
+ %2(s32) = G_ANYEXT %0(s1)
+ %3(s32) = G_ANYEXT %1(s1)
+ %4(s32) = G_ADD %2, %3
+ %5(s1) = G_TRUNC %4(s32)
+ %r0 = COPY %5(s1)
BX_RET 14, _, implicit %r0
...
@@ -178,19 +205,28 @@ selected: false
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
%1(s16) = COPY %r1
- %2(s16) = G_SUB %0, %1
- %r0 = COPY %2(s16)
+ %2(s32) = G_ANYEXT %0(s16)
+ %3(s32) = G_ANYEXT %1(s16)
+ %4(s32) = G_SUB %2, %3
+ %5(s16) = G_TRUNC %4(s32)
+ %r0 = COPY %5(s16)
BX_RET 14, _, implicit %r0
...
@@ -204,19 +240,28 @@ selected: false
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
%1(s8) = COPY %r1
- %2(s8) = G_SUB %0, %1
- %r0 = COPY %2(s8)
+ %2(s32) = G_ANYEXT %0(s8)
+ %3(s32) = G_ANYEXT %1(s8)
+ %4(s32) = G_SUB %2, %3
+ %5(s8) = G_TRUNC %4(s32)
+ %r0 = COPY %5(s8)
BX_RET 14, _, implicit %r0
...
@@ -256,19 +301,28 @@ selected: false
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s16) = COPY %r0
%1(s16) = COPY %r1
- %2(s16) = G_MUL %0, %1
- %r0 = COPY %2(s16)
+ %2(s32) = G_ANYEXT %0(s16)
+ %3(s32) = G_ANYEXT %1(s16)
+ %4(s32) = G_MUL %2, %3
+ %5(s16) = G_TRUNC %4(s32)
+ %r0 = COPY %5(s16)
BX_RET 14, _, implicit %r0
...
@@ -282,19 +336,28 @@ selected: false
# CHECK: - { id: 0, class: gprb }
# CHECK: - { id: 1, class: gprb }
# CHECK: - { id: 2, class: gprb }
+# CHECK: - { id: 3, class: gprb }
+# CHECK: - { id: 4, class: gprb }
+# CHECK: - { id: 5, class: gprb }
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
+ - { id: 3, class: _ }
+ - { id: 4, class: _ }
+ - { id: 5, class: _ }
body: |
bb.0:
liveins: %r0, %r1
%0(s8) = COPY %r0
%1(s8) = COPY %r1
- %2(s8) = G_MUL %0, %1
- %r0 = COPY %2(s8)
+ %2(s32) = G_ANYEXT %0(s8)
+ %3(s32) = G_ANYEXT %1(s8)
+ %4(s32) = G_MUL %2, %3
+ %5(s8) = G_TRUNC %4(s32)
+ %r0 = COPY %5(s8)
BX_RET 14, _, implicit %r0
...
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