[llvm] r302778 - [ARM][GlobalISel] Support for G_ANYEXT
Diana Picus via llvm-commits
llvm-commits at lists.llvm.org
Thu May 11 01:28:31 PDT 2017
Author: rovka
Date: Thu May 11 03:28:31 2017
New Revision: 302778
URL: http://llvm.org/viewvc/llvm-project?rev=302778&view=rev
Log:
[ARM][GlobalISel] Support for G_ANYEXT
G_ANYEXT can be introduced by the legalizer when widening scalars. Add
support for it in the register bank info (same mapping as everything
else) and in the instruction selector.
When selecting it, we treat it as a COPY, just like G_TRUNC. On this
occasion we get rid of some assertions in selectCopy so we can reuse it.
This shouldn't be a problem at the moment since we're not supporting any
complicated cases (e.g. FPR, different register banks). We might want to
separate the paths when we do.
Modified:
llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
Modified: llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp?rev=302778&r1=302777&r2=302778&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMInstructionSelector.cpp Thu May 11 03:28:31 2017
@@ -101,14 +101,6 @@ static bool selectCopy(MachineInstr &I,
assert(RegBank && "Can't get reg bank for virtual register");
const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
- (void)DstSize;
- unsigned SrcReg = I.getOperand(1).getReg();
- const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
- (void)SrcSize;
- // We use copies for trunc, so it's ok for the size of the destination to be
- // smaller (the higher bits will just be undefined).
- assert(DstSize <= SrcSize && "Copy with different width?!");
-
assert((RegBank->getID() == ARM::GPRRegBankID ||
RegBank->getID() == ARM::FPRRegBankID) &&
"Unsupported reg bank");
@@ -330,6 +322,7 @@ bool ARMInstructionSelector::select(Mach
}
break;
}
+ case G_ANYEXT:
case G_TRUNC: {
// The high bits are undefined, so there's nothing special to do, just
// treat it as a copy.
@@ -340,12 +333,12 @@ bool ARMInstructionSelector::select(Mach
const auto &DstRegBank = *RBI.getRegBank(DstReg, MRI, TRI);
if (SrcRegBank.getID() != DstRegBank.getID()) {
- DEBUG(dbgs() << "G_TRUNC operands on different register banks\n");
+ DEBUG(dbgs() << "G_TRUNC/G_ANYEXT operands on different register banks\n");
return false;
}
if (SrcRegBank.getID() != ARM::GPRRegBankID) {
- DEBUG(dbgs() << "G_TRUNC on non-GPR not supported yet\n");
+ DEBUG(dbgs() << "G_TRUNC/G_ANYEXT on non-GPR not supported yet\n");
return false;
}
Modified: llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp?rev=302778&r1=302777&r2=302778&view=diff
==============================================================================
--- llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/ARM/ARMRegisterBankInfo.cpp Thu May 11 03:28:31 2017
@@ -225,6 +225,7 @@ ARMRegisterBankInfo::getInstrMapping(con
case G_UDIV:
case G_SEXT:
case G_ZEXT:
+ case G_ANYEXT:
case G_TRUNC:
case G_GEP:
// FIXME: We're abusing the fact that everything lives in a GPR for now; in
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir?rev=302778&r1=302777&r2=302778&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir Thu May 11 03:28:31 2017
@@ -4,6 +4,8 @@
define void @test_sext_s1() { ret void }
define void @test_sext_s8() { ret void }
define void @test_zext_s16() { ret void }
+ define void @test_anyext_s8() { ret void }
+ define void @test_anyext_s16() { ret void }
define void @test_trunc_s32_16() { ret void }
@@ -144,6 +146,58 @@ body: |
%r0 = COPY %1(s32)
; CHECK: %r0 = COPY [[VREGEXT]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_anyext_s8
+# CHECK-LABEL: name: test_anyext_s8
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s8) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+ %1(s32) = G_ANYEXT %0(s8)
+ ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGX]]
+
+ %r0 = COPY %1(s32)
+ ; CHECK: %r0 = COPY [[VREGEXT]]
+
+ BX_RET 14, _, implicit %r0
+ ; CHECK: BX_RET 14, _, implicit %r0
+...
+---
+name: test_anyext_s16
+# CHECK-LABEL: name: test_anyext_s16
+legalized: true
+regBankSelected: true
+selected: false
+# CHECK: selected: true
+registers:
+ - { id: 0, class: gprb }
+ - { id: 1, class: gprb }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s16) = COPY %r0
+ ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
+
+ %1(s32) = G_ANYEXT %0(s16)
+ ; CHECK: [[VREGEXT:%[0-9]+]] = COPY [[VREGX]]
+
+ %r0 = COPY %1(s32)
+ ; CHECK: %r0 = COPY [[VREGEXT]]
BX_RET 14, _, implicit %r0
; CHECK: BX_RET 14, _, implicit %r0
Modified: llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir?rev=302778&r1=302777&r2=302778&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/ARM/GlobalISel/arm-regbankselect.mir Thu May 11 03:28:31 2017
@@ -25,6 +25,9 @@
define void @test_constants() { ret void }
+ define void @test_anyext_s8_32() { ret void }
+ define void @test_anyext_s16_32() { ret void }
+
define void @test_trunc_s32_16() { ret void }
define void @test_fadd_s32() #0 { ret void }
@@ -500,6 +503,48 @@ body: |
BX_RET 14, _, implicit %r0
...
---
+name: test_anyext_s8_32
+# CHECK-LABEL: name: test_anyext_s8_32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s8) = COPY %r0
+ %1(s32) = G_ANYEXT %0(s8)
+ %r0 = COPY %1(s32)
+ BX_RET 14, _, implicit %r0
+...
+---
+name: test_anyext_s16_32
+# CHECK-LABEL: name: test_anyext_s16_32
+legalized: true
+regBankSelected: false
+selected: false
+# CHECK: registers:
+# CHECK: - { id: 0, class: gprb }
+# CHECK: - { id: 1, class: gprb }
+registers:
+ - { id: 0, class: _ }
+ - { id: 1, class: _ }
+body: |
+ bb.0:
+ liveins: %r0
+
+ %0(s16) = COPY %r0
+ %1(s32) = G_ANYEXT %0(s16)
+ %r0 = COPY %1(s32)
+ BX_RET 14, _, implicit %r0
+...
+---
name: test_trunc_s32_16
# CHECK-LABEL: name: test_trunc_s32_16
legalized: true
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