[PATCH] D33086: [AMDGPU] Fix incorrect register pressure calculation

Stanislav Mekhanoshin via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed May 10 19:21:33 PDT 2017


rampitec created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, arsenm.

Earlier fix https://reviews.llvm.org/D32572 introduced a bug where live-ins were calculated
for basic block instead of scheduling region. This change fixes it.


Repository:
  rL LLVM

https://reviews.llvm.org/D33086

Files:
  lib/Target/AMDGPU/GCNSchedStrategy.cpp


Index: lib/Target/AMDGPU/GCNSchedStrategy.cpp
===================================================================
--- lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -422,9 +422,12 @@
   unsigned SGPRs = 0;
   unsigned VGPRs = 0;
 
-  auto &MI = *begin()->getParent()->getFirstNonDebugInstr();
+  auto I = begin();
+  for (auto const E = I->getParent()->end(); I != E; ++I)
+    if (!I->isDebugValue())
+      break;
   const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI);
-  SlotIndex SI = LIS->getInstructionIndex(MI).getBaseIndex();
+  SlotIndex SI = LIS->getInstructionIndex(*I).getBaseIndex();
   assert (SI.isValid());
 
   DEBUG(dbgs() << "Region live-ins:");


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D33086.98574.patch
Type: text/x-patch
Size: 720 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170511/385667fb/attachment.bin>


More information about the llvm-commits mailing list