[PATCH] D33086: [AMDGPU] Fix incorrect register pressure calculation

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec created this revision.
Herald added subscribers: t-tye, tpr, dstuttard, yaxunl, nhaehnle, wdng, arsenm.

Earlier fix https://reviews.llvm.org/D32572 introduced a bug where live-ins were calculated
for basic block instead of scheduling region. This change fixes it.


Repository:
  rL LLVM

https://reviews.llvm.org/D33086

Files:
  lib/Target/AMDGPU/GCNSchedStrategy.cpp


Index: lib/Target/AMDGPU/GCNSchedStrategy.cpp
===================================================================
--- lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -422,9 +422,12 @@
   unsigned SGPRs = 0;
   unsigned VGPRs = 0;
 
-  auto &MI = *begin()->getParent()->getFirstNonDebugInstr();
+  auto I = begin();
+  for (auto const E = I->getParent()->end(); I != E; ++I)
+    if (!I->isDebugValue())
+      break;
   const SIRegisterInfo *SRI = static_cast<const SIRegisterInfo*>(TRI);
-  SlotIndex SI = LIS->getInstructionIndex(MI).getBaseIndex();
+  SlotIndex SI = LIS->getInstructionIndex(*I).getBaseIndex();
   assert (SI.isValid());
 
   DEBUG(dbgs() << "Region live-ins:");


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