[llvm] r302679 - [AArch64][RegisterBankInfo] Change the default mapping of fp stores.

[Quentin Colombet via llvm-commits]

Author: qcolombet
Date: Wed May 10 10:19:41 2017
New Revision: 302679

URL: http://llvm.org/viewvc/llvm-project?rev=302679&view=rev
Log:
[AArch64][RegisterBankInfo] Change the default mapping of fp stores.

For stores, check if the stored value is defined by a floating point
instruction and if yes, we return a default mapping with FPR instead
of GPR.

Modified:
    llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
    llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir

Modified: llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp?rev=302679&r1=302678&r2=302679&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp (original)
+++ llvm/trunk/lib/Target/AArch64/AArch64RegisterBankInfo.cpp Wed May 10 10:19:41 2017
@@ -546,6 +546,17 @@ AArch64RegisterBankInfo::getInstrMapping
           break;
         }
     break;
+  case TargetOpcode::G_STORE:
+    // Check if that store is fed by fp instructions.
+    if (OpRegBankIdx[0] == PMI_FirstGPR) {
+      unsigned VReg = MI.getOperand(0).getReg();
+      if (!VReg)
+        break;
+      MachineInstr *DefMI = MRI.getVRegDef(VReg);
+      if (isPreISelGenericFloatingPointOpcode(DefMI->getOpcode()))
+        OpRegBankIdx[0] = PMI_FirstFPR;
+      break;
+    }
   }
 
   // Finally construct the computed mapping.

Modified: llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir?rev=302679&r1=302678&r2=302679&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir (original)
+++ llvm/trunk/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir Wed May 10 10:19:41 2017
@@ -82,6 +82,13 @@
     %res = bitcast double %vres to i64
     ret i64 %res
   }
+
+  define void @floatingPointStore(i64 %arg1, double* %addr) {
+    %varg1 = bitcast i64 %arg1 to double
+    %vres = fadd double %varg1, %varg1
+    store double %vres, double* %addr
+    ret void
+  }
 ...
 
 ---
@@ -700,3 +707,42 @@ body:             |
     RET_ReallyLR implicit %x0
 
 ...
+
+---
+# Make sure we map what looks like floating point
+# stores to floating point register bank.
+# CHECK-LABEL: name: floatingPointStore
+name:            floatingPointStore
+legalized:       true
+
+# CHECK: registers:
+# CHECK-NEXT:  - { id: 0, class: gpr }
+# CHECK-NEXT:  - { id: 1, class: gpr }
+# CHECK-NEXT:   - { id: 2, class: fpr }
+# CHECK-NEXT:   - { id: 3, class: fpr }
+# CHECK-NEXT:   - { id: 4, class: fpr }
+registers:
+  - { id: 0, class: _ }
+  - { id: 1, class: _ }
+  - { id: 2, class: _ }
+
+# CHECK:         %0(s64) = COPY %x0
+# CHECK-NEXT:    %1(p0) = COPY %x1
+# %0 has been mapped to GPR, we need to repair to match FPR.
+# CHECK-NEXT:    %3(s64) = COPY %0
+# CHECK-NEXT:    %4(s64) = COPY %0
+# CHECK-NEXT:    %2(s64) = G_FADD %3, %4
+# CHECK-NEXT:    G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
+# CHECK-NEXT:    RET_ReallyLR
+
+body:             |
+  bb.0:
+    liveins: %x0, %x1
+
+    %0(s64) = COPY %x0
+    %1(p0) = COPY %x1
+    %2(s64) = G_FADD %0, %0
+    G_STORE %2(s64), %1(p0) :: (store 8 into %ir.addr)
+    RET_ReallyLR
+
+...