[llvm] r302667 - [SystemZ] Add miscellaneous instructions
Ulrich Weigand via llvm-commits
llvm-commits at lists.llvm.org
Wed May 10 07:20:15 PDT 2017
Author: uweigand
Date: Wed May 10 09:20:15 2017
New Revision: 302667
URL: http://llvm.org/viewvc/llvm-project?rev=302667&view=rev
Log:
[SystemZ] Add miscellaneous instructions
This adds a few missing instructions for the assembler and
disassembler. Those should be the last missing general-
purpose (Chapter 7) instructions for the z10 ISA.
Modified:
llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
llvm/trunk/test/MC/SystemZ/insn-bad.s
llvm/trunk/test/MC/SystemZ/insn-good.s
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrFormats.td Wed May 10 09:20:15 2017
@@ -1627,6 +1627,9 @@ class ICV<string name>
// Inherent:
// One register output operand and no input operands.
//
+// InherentDual:
+// Two register output operands and no input operands.
+//
// StoreInherent:
// One address operand. The instruction stores to the address.
//
@@ -1752,6 +1755,10 @@ class InherentRRE<string mnemonic, bits<
let R2 = 0;
}
+class InherentDualRRE<string mnemonic, bits<16> opcode, RegisterOperand cls>
+ : InstRRE<opcode, (outs cls:$R1, cls:$R2), (ins),
+ mnemonic#"\t$R1, $R2", []>;
+
class InherentVRIa<string mnemonic, bits<16> opcode, bits<16> value>
: InstVRIa<opcode, (outs VR128:$V1), (ins), mnemonic#"\t$V1", []> {
let I2 = value;
@@ -2668,6 +2675,10 @@ class SideEffectBinaryIE<string mnemonic
: InstIE<opcode, (outs), (ins imm1:$I1, imm2:$I2),
mnemonic#"\t$I1, $I2", []>;
+class SideEffectBinarySI<string mnemonic, bits<8> opcode, Operand imm>
+ : InstSI<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
+ mnemonic#"\t$BD1, $I2", []>;
+
class SideEffectBinarySIL<string mnemonic, bits<16> opcode,
SDPatternOperator operator, Immediate imm>
: InstSIL<opcode, (outs), (ins bdaddr12only:$BD1, imm:$I2),
Modified: llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZInstrInfo.td Wed May 10 09:20:15 2017
@@ -1874,10 +1874,31 @@ let mayLoad = 1, Defs = [CC], Uses = [R0
let mayLoad = 1, Defs = [CC], Uses = [R0L, R1L] in
def CUSE : SideEffectBinaryMemMemRRE<"cuse", 0xB257, GR128, GR128>;
+// Compare and form codeword.
+let mayLoad = 1, Defs = [CC, R1D, R2D, R3D], Uses = [R1D, R2D, R3D] in
+ def CFC : SideEffectAddressS<"cfc", 0xB21A, null_frag>;
+
+// Update tree.
+let mayLoad = 1, mayStore = 1, Defs = [CC, R0D, R1D, R2D, R3D, R5D],
+ Uses = [R0D, R1D, R2D, R3D, R4D, R5D] in
+ def UPT : SideEffectInherentE<"upt", 0x0102>;
+
+// Checksum.
+let mayLoad = 1, Defs = [CC] in
+ def CKSM : SideEffectBinaryMemMemRRE<"cksm", 0xB241, GR64, GR128>;
+
+// Compression call.
+let mayLoad = 1, mayStore = 1, Defs = [CC, R1D], Uses = [R0L, R1D] in
+ def CMPSC : SideEffectBinaryMemMemRRE<"cmpsc", 0xB263, GR128, GR128>;
+
// Supervisor call.
let hasSideEffects = 1, isCall = 1, Defs = [CC] in
def SVC : SideEffectUnaryI<"svc", 0x0A, imm32zx8>;
+// Monitor call.
+let hasSideEffects = 1, isCall = 1 in
+ def MC : SideEffectBinarySI<"mc", 0xAF, imm32zx8>;
+
// Store clock.
let hasSideEffects = 1, Defs = [CC] in {
def STCK : StoreInherentS<"stck", 0xB205, null_frag, 8>;
@@ -1889,10 +1910,18 @@ let hasSideEffects = 1, Defs = [CC] in {
let hasSideEffects = 1, Uses = [R0D], Defs = [R0D, CC] in
def STFLE : StoreInherentS<"stfle", 0xB2B0, null_frag, 0>;
+// Extract CPU attribute.
+let hasSideEffects = 1 in
+ def ECAG : BinaryRSY<"ecag", 0xEB4C, null_frag, GR64>;
+
// Extract CPU time.
let Defs = [R0D, R1D], hasSideEffects = 1, mayLoad = 1 in
def ECTG : SideEffectTernarySSF<"ectg", 0xC81, GR64>;
+// Extract PSW.
+let hasSideEffects = 1, Uses = [CC] in
+ def EPSW : InherentDualRRE<"epsw", 0xB98D, GR32>;
+
// Execute.
let hasSideEffects = 1 in {
def EX : SideEffectBinaryRX<"ex", 0x44, GR64>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ13.td Wed May 10 09:20:15 2017
@@ -695,12 +695,27 @@ def : InstRW<[FXa, LSU, Lat30], (instreg
def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
+// Various complex instructions
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CFC$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>;
+
// Move with key
def : InstRW<[FXa, FXa, FXb, LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
+// Monitor call
+def : InstRW<[FXb], (instregex "MC$")>;
+
+// Extract CPU attribute
+def : InstRW<[FXb, Lat30], (instregex "ECAG$")>;
+
// Extract CPU Time
def : InstRW<[FXa, Lat5, LSU], (instregex "ECTG$")>;
+// Extract PSW
+def : InstRW<[FXb, Lat30], (instregex "EPSW$")>;
+
// Execute
def : InstRW<[FXb, GroupAlone], (instregex "EX(RL)?$")>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZ196.td Wed May 10 09:20:15 2017
@@ -628,12 +628,27 @@ def : InstRW<[FXU, LSU, Lat30], (instreg
def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
+// Various complex instructions
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CFC$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>;
+
// Move with key
def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
+// Monitor call
+def : InstRW<[FXU], (instregex "MC$")>;
+
+// Extract CPU attribute
+def : InstRW<[FXU, Lat30], (instregex "ECAG$")>;
+
// Extract CPU Time
def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
+// Extract PSW
+def : InstRW<[FXU, Lat30], (instregex "EPSW$")>;
+
// Execute
def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
Modified: llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td (original)
+++ llvm/trunk/lib/Target/SystemZ/SystemZScheduleZEC12.td Wed May 10 09:20:15 2017
@@ -666,12 +666,27 @@ def : InstRW<[FXU, LSU, Lat30], (instreg
def : InstRW<[LSU, Lat30], (instregex "SRSTU$")>;
def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>;
+// Various complex instructions
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CFC$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "UPT$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CKSM$")>;
+def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CMPSC$")>;
+
// Move with key
def : InstRW<[LSU, Lat8, GroupAlone], (instregex "MVCK$")>;
+// Monitor call
+def : InstRW<[FXU], (instregex "MC$")>;
+
+// Extract CPU attribute
+def : InstRW<[FXU, Lat30], (instregex "ECAG$")>;
+
// Extract CPU Time
def : InstRW<[FXU, Lat5, LSU], (instregex "ECTG$")>;
+// Extract PSW
+def : InstRW<[FXU, Lat30], (instregex "EPSW$")>;
+
// Execute
def : InstRW<[LSU, GroupAlone], (instregex "EX(RL)?$")>;
Modified: llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt (original)
+++ llvm/trunk/test/MC/Disassembler/SystemZ/insns.txt Wed May 10 09:20:15 2017
@@ -1708,6 +1708,24 @@
# CHECK: celgbr %f15, 0, %r0, 1
0xb3 0xa0 0x01 0xf0
+# CHECK: cfc 0
+0xb2 0x1a 0x00 0x00
+
+# CHECK: cfc 0(%r1)
+0xb2 0x1a 0x10 0x00
+
+# CHECK: cfc 0(%r15)
+0xb2 0x1a 0xf0 0x00
+
+# CHECK: cfc 4095
+0xb2 0x1a 0x0f 0xff
+
+# CHECK: cfc 4095(%r1)
+0xb2 0x1a 0x1f 0xff
+
+# CHECK: cfc 4095(%r15)
+0xb2 0x1a 0xff 0xff
+
# CHECK: cfdbr %r0, 0, %f0
0xb3 0x99 0x00 0x00
@@ -2554,6 +2572,18 @@
# CHECK: citle %r0, 0
0xec 0x00 0x00 0x00 0xc0 0x72
+# CHECK: cksm %r0, %r0
+0xb2 0x41 0x00 0x00
+
+# CHECK: cksm %r0, %r14
+0xb2 0x41 0x00 0x0e
+
+# CHECK: cksm %r15, %r0
+0xb2 0x41 0x00 0xf0
+
+# CHECK: cksm %r6, %r8
+0xb2 0x41 0x00 0x68
+
# CHECK: cl %r0, 0
0x55 0x00 0x00 0x00
@@ -3607,6 +3637,18 @@
# CHECK: cly %r15, 0
0xe3 0xf0 0x00 0x00 0x00 0x55
+# CHECK: cmpsc %r0, %r0
+0xb2 0x63 0x00 0x00
+
+# CHECK: cmpsc %r0, %r14
+0xb2 0x63 0x00 0x0e
+
+# CHECK: cmpsc %r14, %r0
+0xb2 0x63 0x00 0xe0
+
+# CHECK: cmpsc %r6, %r8
+0xb2 0x63 0x00 0x68
+
# CHECK: cp 0(1), 0(1)
0xf9 0x00 0x00 0x00 0x00 0x00
@@ -4675,6 +4717,45 @@
# CHECK: ear %r15, %a15
0xb2 0x4f 0x00 0xff
+# CHECK: ecag %r0, %r0, 0
+0xeb 0x00 0x00 0x00 0x00 0x4c
+
+# CHECK: ecag %r0, %r15, 0
+0xeb 0x0f 0x00 0x00 0x00 0x4c
+
+# CHECK: ecag %r14, %r15, 0
+0xeb 0xef 0x00 0x00 0x00 0x4c
+
+# CHECK: ecag %r15, %r15, 0
+0xeb 0xff 0x00 0x00 0x00 0x4c
+
+# CHECK: ecag %r0, %r0, -524288
+0xeb 0x00 0x00 0x00 0x80 0x4c
+
+# CHECK: ecag %r0, %r0, -1
+0xeb 0x00 0x0f 0xff 0xff 0x4c
+
+# CHECK: ecag %r0, %r0, 0
+0xeb 0x00 0x00 0x00 0x00 0x4c
+
+# CHECK: ecag %r0, %r0, 1
+0xeb 0x00 0x00 0x01 0x00 0x4c
+
+# CHECK: ecag %r0, %r0, 524287
+0xeb 0x00 0x0f 0xff 0x7f 0x4c
+
+# CHECK: ecag %r0, %r0, 0(%r1)
+0xeb 0x00 0x10 0x00 0x00 0x4c
+
+# CHECK: ecag %r0, %r0, 0(%r15)
+0xeb 0x00 0xf0 0x00 0x00 0x4c
+
+# CHECK: ecag %r0, %r0, 524287(%r1)
+0xeb 0x00 0x1f 0xff 0x7f 0x4c
+
+# CHECK: ecag %r0, %r0, 524287(%r15)
+0xeb 0x00 0xff 0xff 0x7f 0x4c
+
# CHECK: ectg 0, 0, %r0
0xc8 0x01 0x00 0x00 0x00 0x00
@@ -4777,6 +4858,18 @@
# CHECK: efpc %r15
0xb3 0x8c 0x00 0xf0
+# CHECK: epsw %r0, %r0
+0xb9 0x8d 0x00 0x00
+
+# CHECK: epsw %r0, %r15
+0xb9 0x8d 0x00 0x0f
+
+# CHECK: epsw %r15, %r0
+0xb9 0x8d 0x00 0xf0
+
+# CHECK: epsw %r6, %r8
+0xb9 0x8d 0x00 0x68
+
# CHECK: etnd %r0
0xb2 0xec 0x00 0x00
@@ -8176,6 +8269,27 @@
# CHECK: maebr %f15, %f15, %f15
0xb3 0x0e 0xf0 0xff
+# CHECK: mc 0, 0
+0xaf 0x00 0x00 0x00
+
+# CHECK: mc 4095, 0
+0xaf 0x00 0x0f 0xff
+
+# CHECK: mc 0, 255
+0xaf 0xff 0x00 0x00
+
+# CHECK: mc 0(%r1), 42
+0xaf 0x2a 0x10 0x00
+
+# CHECK: mc 0(%r15), 42
+0xaf 0x2a 0xf0 0x00
+
+# CHECK: mc 4095(%r1), 42
+0xaf 0x2a 0x1f 0xff
+
+# CHECK: mc 4095(%r15), 42
+0xaf 0x2a 0xff 0xff
+
# CHECK: mdb %f0, 0
0xed 0x00 0x00 0x00 0x00 0x1c
@@ -13237,6 +13351,9 @@
# CHECK: unpku 0(256,%r15), 0
0xe2 0xff 0xf0 0x00 0x00 0x00
+# CHECK: upt
+0x01 0x02
+
# CHECK: x %r0, 0
0x57 0x00 0x00 0x00
Modified: llvm/trunk/test/MC/SystemZ/insn-bad.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-bad.s?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-bad.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-bad.s Wed May 10 09:20:15 2017
@@ -720,6 +720,17 @@
celgbr %f0, 0, %r0, 0
#CHECK: error: invalid operand
+#CHECK: cfc -1
+#CHECK: error: invalid operand
+#CHECK: cfc 4096
+#CHECK: error: invalid use of indexed addressing
+#CHECK: cfc 0(%r1,%r2)
+
+ cfc -1
+ cfc 4096
+ cfc 0(%r1,%r2)
+
+#CHECK: error: invalid operand
#CHECK: cfdbr %r0, -1, %f0
#CHECK: error: invalid operand
#CHECK: cfdbr %r0, 16, %f0
@@ -1116,6 +1127,11 @@
citno %r0, 0
cito %r0, 0
+#CHECK: error: invalid register pair
+#CHECK: cksm %r0, %r1
+
+ cksm %r0, %r1
+
#CHECK: error: invalid operand
#CHECK: cl %r0, -1
#CHECK: error: invalid operand
@@ -1621,6 +1637,14 @@
cly %r0, -524289
cly %r0, 524288
+#CHECK: error: invalid register pair
+#CHECK: cmpsc %r1, %r0
+#CHECK: error: invalid register pair
+#CHECK: cmpsc %r0, %r1
+
+ cmpsc %r1, %r0
+ cmpsc %r0, %r1
+
#CHECK: error: missing length in address
#CHECK: cp 0, 0(1)
#CHECK: error: missing length in address
@@ -2143,6 +2167,17 @@
dxbr %f0, %f2
dxbr %f2, %f0
+#CHECK: error: invalid operand
+#CHECK: ecag %r0, %r0, -524289
+#CHECK: error: invalid operand
+#CHECK: ecag %r0, %r0, 524288
+#CHECK: error: invalid use of indexed addressing
+#CHECK: ecag %r0, %r0, 0(%r1,%r2)
+
+ ecag %r0, %r0, -524289
+ ecag %r0, %r0, 524288
+ ecag %r0, %r0, 0(%r1,%r2)
+
#CHECK: error: invalid use of indexed addressing
#CHECK: ectg 160(%r1,%r15),160(%r15), %r2
#CHECK: error: invalid operand
@@ -3205,6 +3240,23 @@
maeb %f0, %f0, 4096
#CHECK: error: invalid operand
+#CHECK: mc -1, 0
+#CHECK: error: invalid operand
+#CHECK: mc 4096, 0
+#CHECK: error: invalid use of indexed addressing
+#CHECK: mc 0(%r1,%r2), 0
+#CHECK: error: invalid operand
+#CHECK: mc 0, -1
+#CHECK: error: invalid operand
+#CHECK: mc 0, 256
+
+ mc -1, 0
+ mc 4096, 0
+ mc 0(%r1,%r2), 0
+ mc 0, -1
+ mc 0, 256
+
+#CHECK: error: invalid operand
#CHECK: mdb %f0, -1
#CHECK: error: invalid operand
#CHECK: mdb %f0, 4096
Modified: llvm/trunk/test/MC/SystemZ/insn-good.s
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/MC/SystemZ/insn-good.s?rev=302667&r1=302666&r2=302667&view=diff
==============================================================================
--- llvm/trunk/test/MC/SystemZ/insn-good.s (original)
+++ llvm/trunk/test/MC/SystemZ/insn-good.s Wed May 10 09:20:15 2017
@@ -2051,6 +2051,20 @@
cegbr %f7, %r8
cegbr %f15, %r15
+#CHECK: cfc 0 # encoding: [0xb2,0x1a,0x00,0x00]
+#CHECK: cfc 0(%r1) # encoding: [0xb2,0x1a,0x10,0x00]
+#CHECK: cfc 0(%r15) # encoding: [0xb2,0x1a,0xf0,0x00]
+#CHECK: cfc 4095 # encoding: [0xb2,0x1a,0x0f,0xff]
+#CHECK: cfc 4095(%r1) # encoding: [0xb2,0x1a,0x1f,0xff]
+#CHECK: cfc 4095(%r15) # encoding: [0xb2,0x1a,0xff,0xff]
+
+ cfc 0
+ cfc 0(%r1)
+ cfc 0(%r15)
+ cfc 4095
+ cfc 4095(%r1)
+ cfc 4095(%r15)
+
#CHECK: cfdbr %r0, 0, %f0 # encoding: [0xb3,0x99,0x00,0x00]
#CHECK: cfdbr %r0, 0, %f15 # encoding: [0xb3,0x99,0x00,0x0f]
#CHECK: cfdbr %r0, 15, %f0 # encoding: [0xb3,0x99,0xf0,0x00]
@@ -3521,6 +3535,16 @@
citnl %r15, 1
citnh %r15, 1
+#CHECK: cksm %r0, %r8 # encoding: [0xb2,0x41,0x00,0x08]
+#CHECK: cksm %r0, %r14 # encoding: [0xb2,0x41,0x00,0x0e]
+#CHECK: cksm %r15, %r0 # encoding: [0xb2,0x41,0x00,0xf0]
+#CHECK: cksm %r15, %r8 # encoding: [0xb2,0x41,0x00,0xf8]
+
+ cksm %r0, %r8
+ cksm %r0, %r14
+ cksm %r15, %r0
+ cksm %r15, %r8
+
#CHECK: cl %r0, 0 # encoding: [0x55,0x00,0x00,0x00]
#CHECK: cl %r0, 4095 # encoding: [0x55,0x00,0x0f,0xff]
#CHECK: cl %r0, 0(%r1) # encoding: [0x55,0x00,0x10,0x00]
@@ -5374,6 +5398,16 @@
cly %r0, 524287(%r15,%r1)
cly %r15, 0
+#CHECK: cmpsc %r0, %r8 # encoding: [0xb2,0x63,0x00,0x08]
+#CHECK: cmpsc %r0, %r14 # encoding: [0xb2,0x63,0x00,0x0e]
+#CHECK: cmpsc %r14, %r0 # encoding: [0xb2,0x63,0x00,0xe0]
+#CHECK: cmpsc %r14, %r8 # encoding: [0xb2,0x63,0x00,0xe8]
+
+ cmpsc %r0, %r8
+ cmpsc %r0, %r14
+ cmpsc %r14, %r0
+ cmpsc %r14, %r8
+
#CHECK: cp 0(1), 0(1) # encoding: [0xf9,0x00,0x00,0x00,0x00,0x00]
#CHECK: cp 0(1), 0(1,%r1) # encoding: [0xf9,0x00,0x00,0x00,0x10,0x00]
#CHECK: cp 0(1), 0(1,%r15) # encoding: [0xf9,0x00,0x00,0x00,0xf0,0x00]
@@ -6461,6 +6495,34 @@
ear %r7, %a8
ear %r15, %a15
+#CHECK: ecag %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x4c]
+#CHECK: ecag %r0, %r15, 0 # encoding: [0xeb,0x0f,0x00,0x00,0x00,0x4c]
+#CHECK: ecag %r14, %r15, 0 # encoding: [0xeb,0xef,0x00,0x00,0x00,0x4c]
+#CHECK: ecag %r15, %r15, 0 # encoding: [0xeb,0xff,0x00,0x00,0x00,0x4c]
+#CHECK: ecag %r0, %r0, -524288 # encoding: [0xeb,0x00,0x00,0x00,0x80,0x4c]
+#CHECK: ecag %r0, %r0, -1 # encoding: [0xeb,0x00,0x0f,0xff,0xff,0x4c]
+#CHECK: ecag %r0, %r0, 0 # encoding: [0xeb,0x00,0x00,0x00,0x00,0x4c]
+#CHECK: ecag %r0, %r0, 1 # encoding: [0xeb,0x00,0x00,0x01,0x00,0x4c]
+#CHECK: ecag %r0, %r0, 524287 # encoding: [0xeb,0x00,0x0f,0xff,0x7f,0x4c]
+#CHECK: ecag %r0, %r0, 0(%r1) # encoding: [0xeb,0x00,0x10,0x00,0x00,0x4c]
+#CHECK: ecag %r0, %r0, 0(%r15) # encoding: [0xeb,0x00,0xf0,0x00,0x00,0x4c]
+#CHECK: ecag %r0, %r0, 524287(%r1) # encoding: [0xeb,0x00,0x1f,0xff,0x7f,0x4c]
+#CHECK: ecag %r0, %r0, 524287(%r15) # encoding: [0xeb,0x00,0xff,0xff,0x7f,0x4c]
+
+ ecag %r0,%r0,0
+ ecag %r0,%r15,0
+ ecag %r14,%r15,0
+ ecag %r15,%r15,0
+ ecag %r0,%r0,-524288
+ ecag %r0,%r0,-1
+ ecag %r0,%r0,0
+ ecag %r0,%r0,1
+ ecag %r0,%r0,524287
+ ecag %r0,%r0,0(%r1)
+ ecag %r0,%r0,0(%r15)
+ ecag %r0,%r0,524287(%r1)
+ ecag %r0,%r0,524287(%r15)
+
#CHECK: ectg 0, 0, %r0 # encoding: [0xc8,0x01,0x00,0x00,0x00,0x00]
#CHECK: ectg 0(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x00,0xf0,0x00]
#CHECK: ectg 1(%r1), 0(%r15), %r2 # encoding: [0xc8,0x21,0x10,0x01,0xf0,0x00]
@@ -6535,6 +6597,16 @@
efpc %r1
efpc %r15
+#CHECK: epsw %r0, %r8 # encoding: [0xb9,0x8d,0x00,0x08]
+#CHECK: epsw %r0, %r15 # encoding: [0xb9,0x8d,0x00,0x0f]
+#CHECK: epsw %r15, %r0 # encoding: [0xb9,0x8d,0x00,0xf0]
+#CHECK: epsw %r15, %r8 # encoding: [0xb9,0x8d,0x00,0xf8]
+
+ epsw %r0, %r8
+ epsw %r0, %r15
+ epsw %r15, %r0
+ epsw %r15, %r8
+
#CHECK: ex %r0, 0 # encoding: [0x44,0x00,0x00,0x00]
#CHECK: ex %r0, 4095 # encoding: [0x44,0x00,0x0f,0xff]
#CHECK: ex %r0, 0(%r1) # encoding: [0x44,0x00,0x10,0x00]
@@ -8766,6 +8838,22 @@
maebr %f7, %f8, %f9
maebr %f15, %f15, %f15
+#CHECK: mc 0, 0 # encoding: [0xaf,0x00,0x00,0x00]
+#CHECK: mc 4095, 0 # encoding: [0xaf,0x00,0x0f,0xff]
+#CHECK: mc 0, 255 # encoding: [0xaf,0xff,0x00,0x00]
+#CHECK: mc 0(%r1), 42 # encoding: [0xaf,0x2a,0x10,0x00]
+#CHECK: mc 0(%r15), 42 # encoding: [0xaf,0x2a,0xf0,0x00]
+#CHECK: mc 4095(%r1), 42 # encoding: [0xaf,0x2a,0x1f,0xff]
+#CHECK: mc 4095(%r15), 42 # encoding: [0xaf,0x2a,0xff,0xff]
+
+ mc 0, 0
+ mc 4095, 0
+ mc 0, 255
+ mc 0(%r1), 42
+ mc 0(%r15), 42
+ mc 4095(%r1), 42
+ mc 4095(%r15), 42
+
#CHECK: mdb %f0, 0 # encoding: [0xed,0x00,0x00,0x00,0x00,0x1c]
#CHECK: mdb %f0, 4095 # encoding: [0xed,0x00,0x0f,0xff,0x00,0x1c]
#CHECK: mdb %f0, 0(%r1) # encoding: [0xed,0x00,0x10,0x00,0x00,0x1c]
@@ -12317,6 +12405,10 @@
unpku 0(256,%r1), 0
unpku 0(256,%r15), 0
+#CHECK: upt # encoding: [0x01,0x02]
+
+ upt
+
#CHECK: x %r0, 0 # encoding: [0x57,0x00,0x00,0x00]
#CHECK: x %r0, 4095 # encoding: [0x57,0x00,0x0f,0xff]
#CHECK: x %r0, 0(%r1) # encoding: [0x57,0x00,0x10,0x00]
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