[PATCH] D14390: [mips] Expansion of LI.S and LI.D

[Daniel Sanders via Phabricator via llvm-commits]

dsanders accepted this revision.
dsanders added a comment.
This revision is now accepted and ready to land.

I haven't looked too closely at the output of the macro since I don't know what it should be but it looks like the issues I raised earlier in the review are no longer there. I just have one nit about nextReg().



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Comment at: lib/Target/Mips/AsmParser/MipsAsmParser.cpp:3007
 
+static unsigned nextReg(unsigned Reg) {
+  if (MipsMCRegisterClasses[Mips::FGR32RegClassID].contains(Reg))
----------------
I'd recommend a comment mentioning the `D0 + 1 == F1` and `F1 + 1 == D1` quirks. It makes sense when you're thinking of it in the context of where it's being used but `F1 + 1 == D1` in particular isn't very obvious without that context. It would be reasonable for a reader to expect `F1 + 1 == F2`.


https://reviews.llvm.org/D14390