[PATCH] D32605: Recognize CTLZ builtin

Joerg Sonnenberger via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue May 9 14:52:01 PDT 2017


joerg added a comment.

That's not true. ARMv4 for example has no clz, it's a V5T feature. That's my point: if the CPU has no direct lowering for the intrinsic, this transform is beneficial only if the resulting intrinsic can be constant folded. But I wonder if we don't catch those cases already with SCEV based optimisations. If a CPU has no direct lowering like on ARMv4, it will add a libcall and with a high chance of being more expensive than the optimisation.


Repository:
  rL LLVM

https://reviews.llvm.org/D32605





More information about the llvm-commits mailing list