[llvm] r302568 - [lanai] Add computeKnownBitsForTargetNode for Lanai.
Jacques Pienaar via llvm-commits
llvm-commits at lists.llvm.org
Tue May 9 11:35:26 PDT 2017
Author: jpienaar
Date: Tue May 9 13:35:26 2017
New Revision: 302568
URL: http://llvm.org/viewvc/llvm-project?rev=302568&view=rev
Log:
[lanai] Add computeKnownBitsForTargetNode for Lanai.
Summary: computeKnownBitsForTargetNode was not defined for Lanai which resulted in additional AND's with 0x1 for the output of SETCC instructions.
Reviewers: eliben, majnemer
Reviewed By: majnemer
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D29605
Added:
llvm/trunk/test/CodeGen/Lanai/masking_setccs.ll
Modified:
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h
llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp?rev=302568&r1=302567&r2=302568&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelLowering.cpp Tue May 9 13:35:26 2017
@@ -11,9 +11,9 @@
//
//===----------------------------------------------------------------------===//
+#include "LanaiISelLowering.h"
#include "Lanai.h"
#include "LanaiCondCode.h"
-#include "LanaiISelLowering.h"
#include "LanaiMachineFunctionInfo.h"
#include "LanaiSubtarget.h"
#include "LanaiTargetObjectFile.h"
@@ -38,10 +38,11 @@
#include "llvm/IR/Function.h"
#include "llvm/IR/GlobalValue.h"
#include "llvm/Support/Casting.h"
-#include "llvm/Support/CommandLine.h"
#include "llvm/Support/CodeGen.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/KnownBits.h"
#include "llvm/Support/MathExtras.h"
#include "llvm/Support/raw_ostream.h"
#include "llvm/Target/TargetCallingConv.h"
@@ -1499,3 +1500,24 @@ SDValue LanaiTargetLowering::PerformDAGC
return SDValue();
}
+
+void LanaiTargetLowering::computeKnownBitsForTargetNode(
+ const SDValue Op, KnownBits &Known, const APInt &DemandedElts,
+ const SelectionDAG &DAG, unsigned Depth) const {
+ unsigned BitWidth = Known.getBitWidth();
+ switch (Op.getOpcode()) {
+ default:
+ break;
+ case LanaiISD::SETCC:
+ Known = KnownBits(BitWidth);
+ Known.Zero.setBits(1, BitWidth);
+ break;
+ case LanaiISD::SELECT_CC:
+ KnownBits Known2;
+ DAG.computeKnownBits(Op->getOperand(0), Known, Depth + 1);
+ DAG.computeKnownBits(Op->getOperand(1), Known2, Depth + 1);
+ Known.Zero &= Known2.Zero;
+ Known.One &= Known2.One;
+ break;
+ }
+}
Modified: llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h?rev=302568&r1=302567&r2=302568&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiISelLowering.h Tue May 9 13:35:26 2017
@@ -106,6 +106,11 @@ public:
SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
+ void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known,
+ const APInt &DemandedElts,
+ const SelectionDAG &DAG,
+ unsigned Depth = 0) const override;
+
private:
SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
CallingConv::ID CallConv, bool IsVarArg,
Modified: llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td?rev=302568&r1=302567&r2=302568&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td (original)
+++ llvm/trunk/lib/Target/Lanai/LanaiInstrInfo.td Tue May 9 13:35:26 2017
@@ -771,9 +771,6 @@ let Uses = [SR] in {
[(set (i32 GPR:$Rs1), (LanaiSetCC imm:$DDDI))]>;
}
-// SCC's output is already 1-bit so and'ing with 1 is redundant.
-def : Pat<(and (LanaiSetCC imm:$DDDI), 1), (SCC imm:$DDDI)>;
-
// Select with hardware support
let Uses = [SR], isSelect = 1 in {
def SELECT : InstRR<0b111, (outs GPR:$Rd),
Added: llvm/trunk/test/CodeGen/Lanai/masking_setccs.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Lanai/masking_setccs.ll?rev=302568&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/Lanai/masking_setccs.ll (added)
+++ llvm/trunk/test/CodeGen/Lanai/masking_setccs.ll Tue May 9 13:35:26 2017
@@ -0,0 +1,48 @@
+; RUN: llc < %s | FileCheck %s
+
+; Test that unnecessary masking with 0x1 is not inserted.
+
+target datalayout = "E-m:e-p:32:32-i64:64-a:0:32-n32-S64"
+target triple = "lanai"
+
+; CHECK-LABEL: masking:
+; CHECK-NOT: mov 1
+define i32 @masking(i32 inreg %a, i32 inreg %b, i32 inreg %c, i32 inreg %d) {
+entry:
+ %cmp = icmp ne i32 %a, 0
+ %cmp1 = icmp ult i32 %a, %b
+ %or.cond = and i1 %cmp, %cmp1
+ br i1 %or.cond, label %return, label %if.end
+
+if.end: ; preds = %entry
+ %cmp2 = icmp ne i32 %b, 0
+ %cmp4 = icmp ult i32 %b, %c
+ %or.cond29 = and i1 %cmp2, %cmp4
+ br i1 %or.cond29, label %return, label %if.end6
+
+if.end6: ; preds = %if.end
+ %cmp7 = icmp ne i32 %c, 0
+ %cmp9 = icmp ult i32 %c, %d
+ %or.cond30 = and i1 %cmp7, %cmp9
+ br i1 %or.cond30, label %return, label %if.end11
+
+if.end11: ; preds = %if.end6
+ %cmp12 = icmp ne i32 %d, 0
+ %cmp14 = icmp ult i32 %d, %a
+ %or.cond31 = and i1 %cmp12, %cmp14
+ %b. = select i1 %or.cond31, i32 %b, i32 21
+ ret i32 %b.
+
+return: ; preds = %if.end6, %if.end, %entry
+ %retval.0 = phi i32 [ %c, %entry ], [ %d, %if.end ], [ %a, %if.end6 ]
+ ret i32 %retval.0
+}
+
+; CHECK-LABEL: notnot:
+; CHECK-NOT: mov 1
+define i32 @notnot(i32 %x) {
+entry:
+ %tobool = icmp ne i32 %x, 0
+ %lnot.ext = zext i1 %tobool to i32
+ ret i32 %lnot.ext
+}
More information about the llvm-commits
mailing list