[PATCH] D32973: [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Mon May 8 11:22:36 PDT 2017
RKSimon added inline comments.
================
Comment at: lib/Target/X86/X86ISelLowering.cpp:21748
+ getZeroVector(VT, Subtarget, DAG, dl), R);
+ } else if (ShiftAmt >= 32) {
// Splat sign to upper i32 dst, and SRA upper i32 src to lower i32.
----------------
delena wrote:
> You don't need "else".
> if VT is v4i64 you need AVX2 to emit the PCMPGT.
> You don't need "else".
OK
> if VT is v4i64 you need AVX2 to emit the PCMPGT.
This is handled by the callers to ArithmeticShiftRight64 further down - I can still add it if you wish?
Repository:
rL LLVM
https://reviews.llvm.org/D32973
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