[PATCH] D32973: [X86][SSE42] Lower v2i64/v4i64 ASHR(X, 63) as PCMPGTQ(0, X)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.

Similar to what we do for vXi8 ASHR(X, 7), use SSE42's PCMPGTQ to splat the sign instead of using the PSRAD+PSHUFD.

Avoiding bitcasts this improves combines that utilize computeNumSignBits, permits memory folding and reduces pipe pressure.

Although it does require a second register, given that this is a (cheap) zero register the impact is minimal.


Repository:
  rL LLVM

https://reviews.llvm.org/D32973

Files:
  lib/Target/X86/X86ISelLowering.cpp
  test/CodeGen/X86/combine-abs.ll
  test/CodeGen/X86/packss.ll
  test/CodeGen/X86/pr32907.ll
  test/CodeGen/X86/vector-pcmp.ll
  test/CodeGen/X86/viabs.ll

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