[PATCH] D32763: [PPC] Lower load acquire/seq_cst trailing fence to cmp + bne + isync.

[Tim Shen via Phabricator via llvm-commits]

timshen added inline comments.


================
Comment at: llvm/test/CodeGen/PowerPC/atomic-2.ll:114
+; CHECK: bne-
+; CHECK: isync
   ret i64 %tmp
----------------
kbarton wrote:
> Please add CHECK-NEXT for the bne- and isync instructions. We want to ensure the cmp, bc, isync instructions stay together. 
I'm not sure about that.

LLVM post-RA scheduler may stick instructions in between the cmp, bc, isync sequence, but the dependencies introduced by cmp and bc are perfectly preserved.


https://reviews.llvm.org/D32763