[PATCH] D32706: [AArch64] Consider widening instructions in cast cost calculation

[Matthew Simpson via Phabricator via llvm-commits]

mssimpso added a comment.

In https://reviews.llvm.org/D32706#745348, @evandro wrote:

> Exynos M1-2 do: 1 cycle for ASIMD ADD and 3 cycles for ASIMD SADDL.  I tried this patch on Exynos and noticed minor regressions and no improvements in a handful of workloads.


OK, yes I see that now. I missed it on the first look! What do you think about adding a new sub-target feature for this then? Something like "FastWideningOps"? We could condition this TTI change on the feature to prevent it from hurting performance on Exynos. And regarding your last point, you could then later use it to guide instruction selection to not generate the widening ops if the non-widening versions (with added extends) are more profitable.


https://reviews.llvm.org/D32706