[llvm] r302110 - [SelectionDAG] Improve known bits support for CTPOP.

[Craig Topper via llvm-commits]

Author: ctopper
Date: Wed May  3 23:33:27 2017
New Revision: 302110

URL: http://llvm.org/viewvc/llvm-project?rev=302110&view=rev
Log:
[SelectionDAG] Improve known bits support for CTPOP.

This is based on the same concept from ValueTracking's version of computeKnownBits.

Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
    llvm/trunk/test/CodeGen/X86/ctpop-combine.ll

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp?rev=302110&r1=302109&r2=302110&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAG.cpp Wed May  3 23:33:27 2017
@@ -2376,7 +2376,10 @@ void SelectionDAG::computeKnownBits(SDVa
     break;
   }
   case ISD::CTPOP: {
-    Known.Zero.setBitsFrom(Log2_32(BitWidth)+1);
+    computeKnownBits(Op.getOperand(0), Known2, DemandedElts, Depth + 1);
+    // If we know some of the bits are zero, they can't be one.
+    unsigned PossibleOnes = BitWidth - Known2.Zero.countPopulation();
+    Known.Zero.setBitsFrom(Log2_32(PossibleOnes) + 1);
     break;
   }
   case ISD::LOAD: {

Modified: llvm/trunk/test/CodeGen/X86/ctpop-combine.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/ctpop-combine.ll?rev=302110&r1=302109&r2=302110&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/X86/ctpop-combine.ll (original)
+++ llvm/trunk/test/CodeGen/X86/ctpop-combine.ll Wed May  3 23:33:27 2017
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown -mcpu=corei7 | FileCheck %s
 
+declare i8 @llvm.ctpop.i8(i8) nounwind readnone
 declare i64 @llvm.ctpop.i64(i64) nounwind readnone
 
 define i32 @test1(i64 %x) nounwind readnone {
@@ -48,3 +49,16 @@ define i32 @test3(i64 %x) nounwind readn
   %conv = zext i1 %cmp to i32
   ret i32 %conv
 }
+
+define i8 @test4(i8 %x) nounwind readnone {
+; CHECK-LABEL: test4:
+; CHECK:       # BB#0:
+; CHECK-NEXT:    andl $127, %edi
+; CHECK-NEXT:    popcntw %di, %ax
+; CHECK-NEXT:    # kill: %AL<def> %AL<kill> %AX<kill>
+; CHECK-NEXT:    retq
+  %x2 = and i8 %x, 127
+  %count = tail call i8 @llvm.ctpop.i8(i8 %x2)
+  %and = and i8 %count, 7
+  ret i8 %and
+}