[llvm] r302073 - [Hexagon] Use automatically-generated scheduling information for HVX
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Wed May 3 13:10:36 PDT 2017
Added: llvm/trunk/lib/Target/Hexagon/HexagonDepTimingClasses.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonDepTimingClasses.h?rev=302073&view=auto
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonDepTimingClasses.h (added)
+++ llvm/trunk/lib/Target/Hexagon/HexagonDepTimingClasses.h Wed May 3 15:10:36 2017
@@ -0,0 +1,132 @@
+//===--- HexagonDepTimingClasses.h ----------------------------------------===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+static bool is_TC3x(unsigned SchedClass) {
+ switch (SchedClass) {
+ case Hexagon::Sched::tc_1000eb10:
+ case Hexagon::Sched::tc_2aaab1e0:
+ case Hexagon::Sched::tc_4997da4a:
+ case Hexagon::Sched::tc_5d806107:
+ case Hexagon::Sched::tc_6264c5e0:
+ case Hexagon::Sched::tc_69bb508b:
+ case Hexagon::Sched::tc_8c8041e6:
+ case Hexagon::Sched::tc_8cb685d9:
+ case Hexagon::Sched::tc_a12a5971:
+ case Hexagon::Sched::tc_ae0722f7:
+ case Hexagon::Sched::tc_ae2c2dc2:
+ case Hexagon::Sched::tc_bc5561d8:
+ case Hexagon::Sched::tc_d6a805a8:
+ case Hexagon::Sched::tc_f055fbb6:
+ case Hexagon::Sched::tc_feb4974b:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_TC2early(unsigned SchedClass) {
+ switch (SchedClass) {
+ case Hexagon::Sched::tc_35fb9d13:
+ case Hexagon::Sched::tc_cbe45117:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_TC4x(unsigned SchedClass) {
+ switch (SchedClass) {
+ case Hexagon::Sched::tc_09c86199:
+ case Hexagon::Sched::tc_2d1e6f5c:
+ case Hexagon::Sched::tc_2e55aa16:
+ case Hexagon::Sched::tc_3bea1824:
+ case Hexagon::Sched::tc_e836c161:
+ case Hexagon::Sched::tc_f1aa2cdb:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_TC2(unsigned SchedClass) {
+ switch (SchedClass) {
+ case Hexagon::Sched::tc_090485bb:
+ case Hexagon::Sched::tc_1fe8323c:
+ case Hexagon::Sched::tc_37326008:
+ case Hexagon::Sched::tc_3c10f809:
+ case Hexagon::Sched::tc_47ab9233:
+ case Hexagon::Sched::tc_485bb57c:
+ case Hexagon::Sched::tc_511f28f6:
+ case Hexagon::Sched::tc_583510c7:
+ case Hexagon::Sched::tc_63cd9d2d:
+ case Hexagon::Sched::tc_76c4c5ef:
+ case Hexagon::Sched::tc_7ca2ea10:
+ case Hexagon::Sched::tc_87601822:
+ case Hexagon::Sched::tc_88fa2da6:
+ case Hexagon::Sched::tc_94e6ffd9:
+ case Hexagon::Sched::tc_ab1b5e74:
+ case Hexagon::Sched::tc_b0f50e3c:
+ case Hexagon::Sched::tc_bd16579e:
+ case Hexagon::Sched::tc_c0cd91a8:
+ case Hexagon::Sched::tc_ca280e8b:
+ case Hexagon::Sched::tc_cd321066:
+ case Hexagon::Sched::tc_d95f4e98:
+ case Hexagon::Sched::tc_e17ce9ad:
+ case Hexagon::Sched::tc_f1240c08:
+ case Hexagon::Sched::tc_faab1248:
+ return true;
+ default:
+ return false;
+ }
+}
+
+static bool is_TC1(unsigned SchedClass) {
+ switch (SchedClass) {
+ case Hexagon::Sched::tc_07ac815d:
+ case Hexagon::Sched::tc_1b6011fb:
+ case Hexagon::Sched::tc_1b834fe7:
+ case Hexagon::Sched::tc_1e062b18:
+ case Hexagon::Sched::tc_1f9668cc:
+ case Hexagon::Sched::tc_43068634:
+ case Hexagon::Sched::tc_47f0b7ad:
+ case Hexagon::Sched::tc_537e2013:
+ case Hexagon::Sched::tc_548f402d:
+ case Hexagon::Sched::tc_5fa2857c:
+ case Hexagon::Sched::tc_5fe9fcd0:
+ case Hexagon::Sched::tc_78b3c689:
+ case Hexagon::Sched::tc_7c2dcd4d:
+ case Hexagon::Sched::tc_81a23d44:
+ case Hexagon::Sched::tc_821c4233:
+ case Hexagon::Sched::tc_92d1833c:
+ case Hexagon::Sched::tc_9a13af9d:
+ case Hexagon::Sched::tc_9c18c9a5:
+ case Hexagon::Sched::tc_9df8b0dc:
+ case Hexagon::Sched::tc_9f518242:
+ case Hexagon::Sched::tc_a1fb80e1:
+ case Hexagon::Sched::tc_a333d2a9:
+ case Hexagon::Sched::tc_a87879e8:
+ case Hexagon::Sched::tc_aad55963:
+ case Hexagon::Sched::tc_b08b653e:
+ case Hexagon::Sched::tc_b324366f:
+ case Hexagon::Sched::tc_b5bfaa60:
+ case Hexagon::Sched::tc_b86c7e8b:
+ case Hexagon::Sched::tc_c58f771a:
+ case Hexagon::Sched::tc_d108a090:
+ case Hexagon::Sched::tc_d1b5a4b6:
+ case Hexagon::Sched::tc_d2609065:
+ case Hexagon::Sched::tc_d63b71d1:
+ case Hexagon::Sched::tc_e2c31426:
+ case Hexagon::Sched::tc_e8c7a357:
+ case Hexagon::Sched::tc_eb07ef6f:
+ case Hexagon::Sched::tc_f16d5b17:
+ return true;
+ default:
+ return false;
+ }
+}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIICHVX.td Wed May 3 15:10:36 2017
@@ -7,96 +7,12 @@
//
//===----------------------------------------------------------------------===//
-//
-// Though all these itinerary classes exist for V60 onwards, they are being
-// listed here as 'HVXV62Itin' because itinerary class description prior to V62
-// doesn't include operand cycle info. In future, I plan to merge them
-// together and call it 'HVXItin'.
-//
-class HVXV62Itin {
- list<InstrItinData> HVXV62Itin_list = [
- InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
- [InstrStage<1, [SLOT0, SLOT1]>],
- [3, 1, 1, 1]>,
- InstrItinData<COPROC_VX_vtc_long_SLOT23,
- [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1, 1]>,
- InstrItinData<COPROC_VX_vtc_SLOT23,
- [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1, 1]>,
- InstrItinData<CVI_VA, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLANE,CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VA_DV, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF, CVI_MPY01]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VX, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VX_DV_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VX_DV, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VX_DV_SLOT2, [InstrStage<1, [SLOT2], 0>,
- InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VX_DV_SLOT2_LONG_EARLY,
- [InstrStage<1, [SLOT2], 0>,
- InstrStage<1, [CVI_MPY01]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VP_VS_EARLY, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VP_VS_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VP_VS, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VP_VS_LONG_EARLY,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VP_DV, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VS, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_SHIFT]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VINLANESAT, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VM_LD, [InstrStage<1, [SLOT0, SLOT1], 0>,
- InstrStage<1, [CVI_LD], 0>,
- InstrStage<1, [CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VM_TMP_LD, [InstrStage<1,[SLOT0, SLOT1], 0>,
- InstrStage<1, [CVI_LD]>],[1, 1, 1, 1, 10]>,
- InstrItinData<CVI_VM_CUR_LD, [InstrStage<1,[SLOT0, SLOT1], 0>,
- InstrStage<1, [CVI_LD], 0>,
- InstrStage<1, [CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VM_VP_LDU, [InstrStage<1,[SLOT0], 0>,
- InstrStage<1, [SLOT1], 0>,
- InstrStage<1, [CVI_LD], 0>,
- InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VM_ST, [InstrStage<1, [SLOT0], 0>,
- InstrStage<1, [CVI_ST], 0>,
- InstrStage<1, [CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>],
- [1, 1, 1, 1]>,
- InstrItinData<CVI_VM_NEW_ST, [InstrStage<1,[SLOT0], 0>,
- InstrStage<1, [CVI_ST]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_VM_STU, [InstrStage<1, [SLOT0], 0>,
- InstrStage<1, [SLOT1], 0>,
- InstrStage<1, [CVI_ST], 0>,
- InstrStage<1, [CVI_XLANE]>], [1, 1, 1, 1]>,
- InstrItinData<CVI_HIST, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_ALL]>], [1, 1, 1, 1]>];
+def CVI_VA : InstrItinClass;
+
+class HVXItin {
+ list<InstrItinData> HVXItin_list = [
+ InstrItinData<CVI_VA,
+ [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
+ InstrStage<1, [CVI_XLANE,CVI_SHIFT, CVI_MPY0, CVI_MPY1]>],
+ [9, 7, 7, 7], [HVX_FWD, HVX_FWD, HVX_FWD]>];
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonIICScalar.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonIICScalar.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonIICScalar.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonIICScalar.td Wed May 3 15:10:36 2017
@@ -11,154 +11,22 @@
// classes as per V62. Curretnly, they are just extracted from
// HexagonScheduleV62.td but will soon be auto-generated by HexagonGen.py.
+class PseudoItin {
+ list<InstrItinData> PseudoItin_list = [
+ InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
+ [1, 1, 1]>,
+ InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
+ InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
+ InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
+ ];
+}
+
class ScalarItin {
list<InstrItinData> ScalarItin_list = [
- InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
- InstrItinData<ALU32_2op_tc_2early_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
- InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
- InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
- InstrItinData<ALU32_3op_tc_2early_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
- InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
-
- // ALU64
- InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
-
- // CR -> System
- InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
- InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
- InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>], [3, 1, 1]>,
-
- // Jump (conditional/unconditional/return etc)
- InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1, 1]>,
- InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1, 1]>,
- InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1, 1]>,
- InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1, 1]>,
- InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1, 1]>,
- InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1, 1]>,
-
- // JR
- InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>], [2, 1, 1]>,
- InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<1, [SLOT2]>], [3, 1, 1]>,
-
- // Extender
- InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1,
- [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1, 1]>,
-
- // Load
- InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [3, 1]>,
- InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [3, 1]>,
- InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [4, 1]>,
- InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [3, 1]>,
-
- // M
- InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1, 1]>,
- InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [4, 1, 1]>,
- InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [4, 1, 1]>,
- InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
-
- // Store
- InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1]>,
- InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1]>,
- InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [3, 1, 1]>,
- InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [3, 1, 1]>,
- InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
- InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
-
- // S
- InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- // The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60.
- InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [4, 1, 1]>,
- InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
-
- // New Value Compare Jump
- InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>],
- [3, 1, 1, 1]>,
-
- // Mem ops
- InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
- [1, 1, 1, 1]>,
- InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [2, 1, 1, 1]>,
- InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1, 1]>,
- InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
- [1, 1, 1, 1]>,
- InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [3, 1, 1, 1]>,
- InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1, 1]>,
-
- // Endloop
- InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>],
- [2]>,
- InstrItinData<MAPPING_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
- [1, 1, 1, 1]>,
-
- // Duplex and Compound
- InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
- InstrItinData<COMPOUND_CJ_ARCHDEPSLOT,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
- InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
- // Misc
- InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<PSEUDOM , [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>];
+ InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
+ [3, 1], [Hex_FWD, Hex_FWD]>,
+ InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
+ [1, 1, 1], [Hex_FWD, Hex_FWD, Hex_FWD]>
+ ];
}
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormats.td Wed May 3 15:10:36 2017
@@ -188,30 +188,10 @@ class LDInst<dag outs, dag ins, string a
string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
-class PseudoLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
-
class CONSTLDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : PseudoLDInst<outs, ins, asmstr, pattern, cstr>;
-
-// LD Instruction Class in V2/V3/V4.
-// Definition of the instruction class NOT CHANGED.
-class LDInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : LDInst<outs, ins, asmstr, pattern, cstr>;
-
-let mayLoad = 1 in
-class LD0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
+ string cstr = "", InstrItinClass itin = LD_tc_ld_SLOT01>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>, OpcodeHexagon;
-let mayLoad = 1 in
-class LD1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin=LD_tc_ld_SLOT0>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeLD>;
-
// ST Instruction Class in V2/V3 can take SLOT0 only.
// ST Instruction Class in V4 can take SLOT0 & SLOT1.
// Definition of the instruction class CHANGED from V2/V3 to V4.
@@ -220,124 +200,9 @@ class STInst<dag outs, dag ins, string a
string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
-let mayStore = 1 in
-class STInst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
-
-class STInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : STInst<outs, ins, asmstr, pattern, cstr>;
-
-let mayStore = 1 in
-class ST0Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ST_tc_ld_SLOT0>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>, OpcodeHexagon;
-
-// Same as ST0Inst but doesn't derive from OpcodeHexagon.
-let mayStore = 1 in
-class ST1Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeST>;
-
-// ST Instruction Class in V2/V3 can take SLOT0 only.
-// ST Instruction Class in V4 can take SLOT0 & SLOT1.
-// Definition of the instruction class CHANGED from V2/V3 to V4.
-class STInstPost<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ST_tc_st_SLOT01>
- : STInst<outs, ins, asmstr, pattern, cstr, itin>;
-
-// ALU64 Instruction Class in V2/V3.
-// XTYPE Instruction Class in V4.
-// Definition of the instruction class NOT CHANGED.
-// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
-class ALU64Inst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU64>,
- OpcodeHexagon;
-
-// ALU64 Instruction Class in V2/V3.
-// XTYPE Instruction Class in V4.
-// Definition of the instruction class NOT CHANGED.
-// Name of the Instruction Class changed from ALU64 to XTYPE from V2/V3 to V4.
-class ALU64Inst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeALU64>;
-
-
-class ALU64_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU64_tc_2_SLOT23>
- : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
-
-
-// M Instruction Class in V2/V3.
-// XTYPE Instruction Class in V4.
-// Definition of the instruction class NOT CHANGED.
-// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
-class MInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeM>,
- OpcodeHexagon;
-
-// Same as above but doesn't derive from OpcodeHexagon
-class MInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = M_tc_3x_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeM>;
-
-// M Instruction Class in V2/V3.
-// XTYPE Instruction Class in V4.
-// Definition of the instruction class NOT CHANGED.
-// Name of the Instruction Class changed from M to XTYPE from V2/V3 to V4.
-class MInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = M_tc_2_SLOT23>
- : MInst<outs, ins, asmstr, pattern, cstr, itin>;
-
-// S Instruction Class in V2/V3.
-// XTYPE Instruction Class in V4.
-// Definition of the instruction class NOT CHANGED.
-// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
-class SInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>,
- OpcodeHexagon;
-
-class SInst_NoOpcode<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>;
-
-class SInst2<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = S_2op_tc_1_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeS_2op>;
-
-// S Instruction Class in V2/V3.
-// XTYPE Instruction Class in V4.
-// Definition of the instruction class NOT CHANGED.
-// Name of the Instruction Class changed from S to XTYPE from V2/V3 to V4.
-class SInst_acc<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = S_3op_tc_1_SLOT23>
- : SInst<outs, ins, asmstr, pattern, cstr, itin> {
- let Type = TypeS_3op;
-}
-
-// J Instruction Class in V2/V3/V4.
-// Definition of the instruction class NOT CHANGED.
-class JInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = J_tc_2early_SLOT23>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
-
-class JInst_CJUMP_UCJUMP<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeJ>, OpcodeHexagon;
-
-// CR Instruction Class in V2/V3/V4.
-// Definition of the instruction class NOT CHANGED.
-class CRInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = CR_tc_2early_SLOT3>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCR>, OpcodeHexagon;
-
let isCodeGenOnly = 1, isPseudo = 1 in
class Endloop<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = J_tc_2early_SLOT0123>
+ string cstr = "", InstrItinClass itin = tc_ENDLOOP>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeENDLOOP>,
OpcodeHexagon;
@@ -357,27 +222,6 @@ class PseudoM<dag outs, dag ins, string
// Instruction Classes Definitions -
//===----------------------------------------------------------------------===//
-//
-// ALU64 patterns.
-//
-class ALU64_rr<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
- : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
-
-class ALU64_ri<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ALU64_tc_1_SLOT23>
- : ALU64Inst<outs, ins, asmstr, pattern, cstr, itin>;
-
-// Post increment ST Instruction.
-class STInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : STInst<outs, ins, asmstr, pattern, cstr>;
-
-// Post increment LD Instruction.
-class LDInstPI<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : LDInst<outs, ins, asmstr, pattern, cstr>;
-
//===----------------------------------------------------------------------===//
// V4 Instruction Format Definitions +
//===----------------------------------------------------------------------===//
@@ -385,7 +229,7 @@ class LDInstPI<dag outs, dag ins, string
include "HexagonInstrFormatsV4.td"
//===----------------------------------------------------------------------===//
-// V4 Instruction Format Definitions +
+// V55 Instruction Format Definitions +
//===----------------------------------------------------------------------===//
//===----------------------------------------------------------------------===//
@@ -395,5 +239,5 @@ include "HexagonInstrFormatsV4.td"
include "HexagonInstrFormatsV60.td"
//===----------------------------------------------------------------------===//
-// V60 Instruction Format Definitions +
+// V62 Instruction Format Definitions +
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV4.td Wed May 3 15:10:36 2017
@@ -1,4 +1,4 @@
-//==- HexagonInstrFormats.td - Hexagon Instruction Formats --*- tablegen -*-==//
+//==- HexagonInstrFormatsV4.td - Hexagon Instruction Formats --*- tablegen -==//
//
// The LLVM Compiler Infrastructure
//
@@ -85,64 +85,3 @@ class InstDuplex<bits<4> iClass, list<da
bits<2> opExtentAlign = 0;
let TSFlags{28-27} = opExtentAlign; // Alignment exponent before extending.
}
-
-//----------------------------------------------------------------------------//
-// Instruction Classes Definitions
-//----------------------------------------------------------------------------//
-
-//
-// NV type instructions.
-//
-class NVInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeNCJ>, OpcodeHexagon;
-
-class NVInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = NCJ_tc_3or4stall_SLOT0>
- : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
-
-// Definition of Post increment new value store.
-class NVInstPost_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
- : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
-
-// Post increment ST Instruction.
-let mayStore = 1 in
-class NVInstPI_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = ST_tc_st_SLOT0>
- : NVInst<outs, ins, asmstr, pattern, cstr, itin>;
-
-// New-value conditional branch.
-class NCJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : NVInst<outs, ins, asmstr, pattern, cstr>;
-
-let mayLoad = 1, mayStore = 1 in
-class MEMInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeV4LDST>,
- OpcodeHexagon;
-
-class MEMInst_V4<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = V4LDST_tc_st_SLOT0>
- : MEMInst<outs, ins, asmstr, pattern, cstr, itin>;
-
-class EXTENDERInst<dag outs, dag ins, string asmstr, list<dag> pattern = []>
- : InstHexagon<outs, ins, asmstr, pattern, "", EXTENDER_tc_1_SLOT0123,
- TypeEXTENDER>, OpcodeHexagon;
-
-class SUBInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : InstHexagon<outs, ins, asmstr, pattern, "", PREFIX, TypeDUPLEX>,
- OpcodeHexagon;
-
-class CJInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND_CJ_ARCHDEPSLOT, TypeCJ>,
- OpcodeHexagon;
-
-class CJInst_JMPSET<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "">
- : InstHexagon<outs, ins, asmstr, pattern, cstr, COMPOUND, TypeCJ>,
- OpcodeHexagon;
-
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrFormatsV60.td Wed May 3 15:10:36 2017
@@ -20,183 +20,3 @@ class CVI_VA_Resource<dag outs, dag ins,
InstrItinClass itin = CVI_VA>
: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VA_DV_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VA_DV>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA_DV>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VX_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VX_LONG>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VX_Resource_late<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VX_LATE>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
- Requires<[HasV60T, UseHVX]>;
-
-class CVI_VX_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VX>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VX_DV_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VX_DV>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VX_DV_Slot2_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VX_DV_SLOT2>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VX_DV_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VX_DV_LONG>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VP_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VP_LONG>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VP_VS_Resource_early<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VP_VS_EARLY>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VP_VS_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VP_VS_LONG>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VP_VS_Resource_long_early<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VP_VS_LONG_EARLY>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VP_VS>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VS_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VS>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VS>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VINLANESAT_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VINLANESAT>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VINLANESAT>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VS_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VS>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VS>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_LD_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_LD>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_LD>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_LD_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_LD>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_LD>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_TMP_LD_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_TMP_LD>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_TMP_LD>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_TMP_LD_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_TMP_LD>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_TMP_LD>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_VP_LDU_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_VP_LDU>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_VP_LDU>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_VP_LDU_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_VP_LDU>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_VP_LDU>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_ST_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_ST>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_ST>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_ST_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_ST>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_ST>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_NEW_ST_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_NEW_ST>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_NEW_ST>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_NEW_ST_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_NEW_ST>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_NEW_ST>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_STU_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_STU>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_STU>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VM_STU_Resource_long<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VM_STU>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VM_STU>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_HIST_Resource<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_HIST>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
- OpcodeHexagon, Requires<[HasV60T, UseHVX]>;
-
-class CVI_VA_Resource1<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VA>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VA>,
- Requires<[HasV60T, UseHVX]>;
-
-class CVI_VX_DV_Resource1<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_VX_DV>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_VX_DV>,
- Requires<[HasV60T, UseHVX]>;
-
-class CVI_HIST_Resource1<dag outs, dag ins, string asmstr,
- list<dag> pattern = [], string cstr = "",
- InstrItinClass itin = CVI_HIST>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, TypeCVI_HIST>,
- Requires<[HasV60T, UseHVX]>;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.cpp Wed May 3 15:10:36 2017
@@ -59,6 +59,7 @@ using namespace llvm;
#define GET_INSTRMAP_INFO
#include "HexagonGenInstrInfo.inc"
#include "HexagonGenDFAPacketizer.inc"
+#include "HexagonDepTimingClasses.h"
cl::opt<bool> ScheduleInlineAsm("hexagon-sched-inline-asm", cl::Hidden,
cl::init(false), cl::desc("Do not consider inline-asm a scheduling/"
@@ -1643,6 +1644,7 @@ unsigned HexagonInstrInfo::getInstrLaten
return getInstrTimingClassLatency(ItinData, MI);
}
+
DFAPacketizer *HexagonInstrInfo::CreateTargetScheduleState(
const TargetSubtargetInfo &STI) const {
const InstrItineraryData *II = STI.getInstrItineraryData();
@@ -2047,9 +2049,7 @@ bool HexagonInstrInfo::isEarlySourceInst
// Multiply
unsigned SchedClass = MI.getDesc().getSchedClass();
- if (SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23)
- return true;
- return false;
+ return is_TC4x(SchedClass) || is_TC3x(SchedClass);
}
bool HexagonInstrInfo::isEndLoopN(unsigned Opcode) const {
@@ -2117,7 +2117,7 @@ bool HexagonInstrInfo::isFloat(const Mac
// No V60 HVX VMEM with A_INDIRECT.
bool HexagonInstrInfo::isHVXMemWithAIndirect(const MachineInstr &I,
const MachineInstr &J) const {
- if (!isV60VectorInstruction(I))
+ if (!isHVXVec(I))
return false;
if (!I.mayLoad() && !I.mayStore())
return false;
@@ -2241,30 +2241,13 @@ bool HexagonInstrInfo::isLateResultInstr
}
unsigned SchedClass = MI.getDesc().getSchedClass();
-
- switch (SchedClass) {
- case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
- case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
- case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
- case Hexagon::Sched::ALU64_tc_1_SLOT23:
- case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
- case Hexagon::Sched::S_2op_tc_1_SLOT23:
- case Hexagon::Sched::S_3op_tc_1_SLOT23:
- case Hexagon::Sched::V2LDST_tc_ld_SLOT01:
- case Hexagon::Sched::V2LDST_tc_st_SLOT0:
- case Hexagon::Sched::V2LDST_tc_st_SLOT01:
- case Hexagon::Sched::V4LDST_tc_ld_SLOT01:
- case Hexagon::Sched::V4LDST_tc_st_SLOT0:
- case Hexagon::Sched::V4LDST_tc_st_SLOT01:
- return false;
- }
- return true;
+ return !is_TC1(SchedClass);
}
bool HexagonInstrInfo::isLateSourceInstr(const MachineInstr &MI) const {
// Instructions with iclass A_CVI_VX and attribute A_CVI_LATE uses a multiply
// resource, but all operands can be received late like an ALU instruction.
- return MI.getDesc().getSchedClass() == Hexagon::Sched::CVI_VX_LATE;
+ return getType(MI) == HexagonII::TypeCVI_VX_LATE;
}
bool HexagonInstrInfo::isLoopN(const MachineInstr &MI) const {
@@ -2507,61 +2490,22 @@ bool HexagonInstrInfo::isTailCall(const
// Returns true when SU has a timing class TC1.
bool HexagonInstrInfo::isTC1(const MachineInstr &MI) const {
unsigned SchedClass = MI.getDesc().getSchedClass();
- switch (SchedClass) {
- case Hexagon::Sched::ALU32_2op_tc_1_SLOT0123:
- case Hexagon::Sched::ALU32_3op_tc_1_SLOT0123:
- case Hexagon::Sched::ALU32_ADDI_tc_1_SLOT0123:
- case Hexagon::Sched::ALU64_tc_1_SLOT23:
- case Hexagon::Sched::EXTENDER_tc_1_SLOT0123:
- //case Hexagon::Sched::M_tc_1_SLOT23:
- case Hexagon::Sched::S_2op_tc_1_SLOT23:
- case Hexagon::Sched::S_3op_tc_1_SLOT23:
- return true;
-
- default:
- return false;
- }
+ return is_TC1(SchedClass);
}
bool HexagonInstrInfo::isTC2(const MachineInstr &MI) const {
unsigned SchedClass = MI.getDesc().getSchedClass();
- switch (SchedClass) {
- case Hexagon::Sched::ALU32_3op_tc_2_SLOT0123:
- case Hexagon::Sched::ALU64_tc_2_SLOT23:
- case Hexagon::Sched::CR_tc_2_SLOT3:
- case Hexagon::Sched::M_tc_2_SLOT23:
- case Hexagon::Sched::S_2op_tc_2_SLOT23:
- case Hexagon::Sched::S_3op_tc_2_SLOT23:
- return true;
-
- default:
- return false;
- }
+ return is_TC2(SchedClass);
}
bool HexagonInstrInfo::isTC2Early(const MachineInstr &MI) const {
unsigned SchedClass = MI.getDesc().getSchedClass();
- switch (SchedClass) {
- case Hexagon::Sched::ALU32_2op_tc_2early_SLOT0123:
- case Hexagon::Sched::ALU32_3op_tc_2early_SLOT0123:
- case Hexagon::Sched::ALU64_tc_2early_SLOT23:
- case Hexagon::Sched::CR_tc_2early_SLOT23:
- case Hexagon::Sched::CR_tc_2early_SLOT3:
- case Hexagon::Sched::J_tc_2early_SLOT0123:
- case Hexagon::Sched::J_tc_2early_SLOT2:
- case Hexagon::Sched::J_tc_2early_SLOT23:
- case Hexagon::Sched::S_2op_tc_2early_SLOT23:
- case Hexagon::Sched::S_3op_tc_2early_SLOT23:
- return true;
-
- default:
- return false;
- }
+ return is_TC2early(SchedClass);
}
bool HexagonInstrInfo::isTC4x(const MachineInstr &MI) const {
unsigned SchedClass = MI.getDesc().getSchedClass();
- return SchedClass == Hexagon::Sched::M_tc_3or4x_SLOT23;
+ return is_TC4x(SchedClass);
}
// Schedule this ASAP.
@@ -2583,7 +2527,7 @@ bool HexagonInstrInfo::isToBeScheduledAS
return false;
}
-bool HexagonInstrInfo::isV60VectorInstruction(const MachineInstr &MI) const {
+bool HexagonInstrInfo::isHVXVec(const MachineInstr &MI) const {
const uint64_t V = getType(MI);
return HexagonII::TypeCVI_FIRST <= V && V <= HexagonII::TypeCVI_LAST;
}
@@ -2782,7 +2726,7 @@ bool HexagonInstrInfo::isValidOffset(uns
}
bool HexagonInstrInfo::isVecAcc(const MachineInstr &MI) const {
- return isV60VectorInstruction(MI) && isAccumulator(MI);
+ return isHVXVec(MI) && isAccumulator(MI);
}
bool HexagonInstrInfo::isVecALU(const MachineInstr &MI) const {
@@ -2888,7 +2832,7 @@ bool HexagonInstrInfo::isZeroExtendingLo
// Add latency to instruction.
bool HexagonInstrInfo::addLatencyToSchedule(const MachineInstr &MI1,
const MachineInstr &MI2) const {
- if (isV60VectorInstruction(MI1) && isV60VectorInstruction(MI2))
+ if (isHVXVec(MI1) && isHVXVec(MI2))
if (!isVecUsableNextPacket(MI1, MI2))
return true;
return false;
@@ -3013,7 +2957,7 @@ bool HexagonInstrInfo::mayBeNewStore(con
bool HexagonInstrInfo::producesStall(const MachineInstr &ProdMI,
const MachineInstr &ConsMI) const {
// There is no stall when ProdMI is not a V60 vector.
- if (!isV60VectorInstruction(ProdMI))
+ if (!isHVXVec(ProdMI))
return false;
// There is no stall when ProdMI and ConsMI are not dependent.
@@ -3031,7 +2975,7 @@ bool HexagonInstrInfo::producesStall(con
bool HexagonInstrInfo::producesStall(const MachineInstr &MI,
MachineBasicBlock::const_instr_iterator BII) const {
// There is no stall when I is not a V60 vector.
- if (!isV60VectorInstruction(MI))
+ if (!isHVXVec(MI))
return false;
MachineBasicBlock::const_instr_iterator MII = BII;
@@ -3415,7 +3359,6 @@ int HexagonInstrInfo::getNonDotCurOp(con
// p.old store
// [if (p0)memw(R0+#0)=R2]
//
-//
// The following set of instructions further explains the scenario where
// conditional new-value store becomes invalid when promoted to .new predicate
// form.
@@ -4025,18 +3968,53 @@ unsigned HexagonInstrInfo::getInstrTimin
if (!ItinData)
return getInstrLatency(ItinData, MI);
- // Get the latency embedded in the itinerary. If we're not using timing class
- // latencies or if we using BSB scheduling, then restrict the maximum latency
- // to 1 (that is, either 0 or 1).
if (MI.isTransient())
return 0;
- unsigned Latency = ItinData->getStageLatency(MI.getDesc().getSchedClass());
- if (!EnableTimingClassLatency ||
- MI.getParent()->getParent()->getSubtarget<HexagonSubtarget>().
- useBSBScheduling())
- if (Latency > 1)
- Latency = 1;
- return Latency;
+ return ItinData->getStageLatency(MI.getDesc().getSchedClass());
+}
+
+/// getOperandLatency - Compute and return the use operand latency of a given
+/// pair of def and use.
+/// In most cases, the static scheduling itinerary was enough to determine the
+/// operand latency. But it may not be possible for instructions with variable
+/// number of defs / uses.
+///
+/// This is a raw interface to the itinerary that may be directly overriden by
+/// a target. Use computeOperandLatency to get the best estimate of latency.
+int HexagonInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
+ const MachineInstr &DefMI,
+ unsigned DefIdx,
+ const MachineInstr &UseMI,
+ unsigned UseIdx) const {
+ auto &RI = getRegisterInfo();
+ // Get DefIdx and UseIdx for super registers.
+ MachineOperand DefMO = DefMI.getOperand(DefIdx);
+
+ if (RI.isPhysicalRegister(DefMO.getReg())) {
+ if (DefMO.isImplicit()) {
+ for (MCSuperRegIterator SR(DefMO.getReg(), &RI); SR.isValid(); ++SR) {
+ int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &RI);
+ if (Idx != -1) {
+ DefIdx = Idx;
+ break;
+ }
+ }
+ }
+
+ MachineOperand UseMO = UseMI.getOperand(UseIdx);
+ if (UseMO.isImplicit()) {
+ for (MCSuperRegIterator SR(UseMO.getReg(), &RI); SR.isValid(); ++SR) {
+ int Idx = UseMI.findRegisterUseOperandIdx(*SR, false, &RI);
+ if (Idx != -1) {
+ UseIdx = Idx;
+ break;
+ }
+ }
+ }
+ }
+
+ return TargetInstrInfo::getOperandLatency(ItinData, DefMI, DefIdx,
+ UseMI, UseIdx);
}
// inverts the predication logic.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonInstrInfo.h Wed May 3 15:10:36 2017
@@ -288,6 +288,19 @@ public:
/// If the instruction is an increment of a constant value, return the amount.
bool getIncrementValue(const MachineInstr &MI, int &Value) const override;
+ /// getOperandLatency - Compute and return the use operand latency of a given
+ /// pair of def and use.
+ /// In most cases, the static scheduling itinerary was enough to determine the
+ /// operand latency. But it may not be possible for instructions with variable
+ /// number of defs / uses.
+ ///
+ /// This is a raw interface to the itinerary that may be directly overriden by
+ /// a target. Use computeOperandLatency to get the best estimate of latency.
+ int getOperandLatency(const InstrItineraryData *ItinData,
+ const MachineInstr &DefMI, unsigned DefIdx,
+ const MachineInstr &UseMI,
+ unsigned UseIdx) const override;
+
bool isTailCall(const MachineInstr &MI) const override;
/// HexagonInstrInfo specifics.
@@ -356,7 +369,7 @@ public:
bool isTC4x(const MachineInstr &MI) const;
bool isToBeScheduledASAP(const MachineInstr &MI1,
const MachineInstr &MI2) const;
- bool isV60VectorInstruction(const MachineInstr &MI) const;
+ bool isHVXVec(const MachineInstr &MI) const;
bool isValidAutoIncImm(const EVT VT, const int Offset) const;
bool isValidOffset(unsigned Opcode, int Offset, bool Extend = true) const;
bool isVecAcc(const MachineInstr &MI) const;
Modified: llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonMachineScheduler.cpp Wed May 3 15:10:36 2017
@@ -744,7 +744,7 @@ int ConvergingVLIWScheduler::SchedulingC
// Give less preference to an instruction that will cause a stall with
// an instruction in the previous packet.
- if (QII.isV60VectorInstruction(Instr)) {
+ if (QII.isHVXVec(Instr)) {
// Check for stalls in the previous packet.
if (Q.getID() == TopQID) {
for (auto J : Top.ResourceModel->OldPacket)
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPatterns.td Wed May 3 15:10:36 2017
@@ -1,13 +1,5 @@
// Pattern fragment that combines the value type and the register class
// into a single parameter.
-// The pat frags in the definitions below need to have a named register,
-// otherwise i32 will be assumed regardless of the register class. The
-// name of the register does not matter.
-def I1 : PatLeaf<(i1 PredRegs:$R)>;
-def I32 : PatLeaf<(i32 IntRegs:$R)>;
-def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
-def F32 : PatLeaf<(f32 IntRegs:$R)>;
-def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
// Pattern fragments to extract the low and high subregisters from a
// 64-bit value.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonPseudo.td Wed May 3 15:10:36 2017
@@ -7,6 +7,15 @@
//
//===----------------------------------------------------------------------===//
+// The pat frags in the definitions below need to have a named register,
+// otherwise i32 will be assumed regardless of the register class. The
+// name of the register does not matter.
+def I1 : PatLeaf<(i1 PredRegs:$R)>;
+def I32 : PatLeaf<(i32 IntRegs:$R)>;
+def I64 : PatLeaf<(i64 DoubleRegs:$R)>;
+def F32 : PatLeaf<(f32 IntRegs:$R)>;
+def F64 : PatLeaf<(f64 DoubleRegs:$R)>;
+
let PrintMethod = "printGlobalOperand" in {
def globaladdress : Operand<i32>;
def globaladdressExt : Operand<i32>;
@@ -23,17 +32,20 @@ def DUPLEX_Pseudo : InstHexagon<(outs),
let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
isAsmParserOnly = 1 in
-def TFRI64_V2_ext : ALU64_rr<(outs DoubleRegs:$dst),
- (ins s32_0Imm:$src1, s8_0Imm:$src2),
- "$dst=combine(#$src1,#$src2)">;
+def TFRI64_V2_ext : InstHexagon<(outs DoubleRegs:$dst),
+ (ins s32_0Imm:$src1, s8_0Imm:$src2),
+ "$dst=combine(#$src1,#$src2)", [], "",
+ A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
// HI/LO Instructions
let isReMaterializable = 1, isMoveImm = 1, hasSideEffects = 0,
hasNewValue = 1, opNewValue = 0 in
-class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp>
+class REG_IMMED<string RegHalf, bit Rs, bits<3> MajOp, bit MinOp,
+ InstHexagon rootInst>
: InstHexagon<(outs IntRegs:$dst),
- (ins u16_0Imm:$imm_value),
- "$dst"#RegHalf#"=#$imm_value", [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>, OpcodeHexagon {
+ (ins u16_0Imm:$imm_value),
+ "$dst"#RegHalf#"=#$imm_value", [], "",
+ rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
bits<5> dst;
bits<32> imm_value;
@@ -46,8 +58,8 @@ class REG_IMMED<string RegHalf, bit Rs,
}
let isAsmParserOnly = 1 in {
- def LO : REG_IMMED<".l", 0b0, 0b001, 0b1>;
- def HI : REG_IMMED<".h", 0b0, 0b010, 0b1>;
+ def LO : REG_IMMED<".l", 0b0, 0b001, 0b1, A2_tfril>;
+ def HI : REG_IMMED<".h", 0b0, 0b010, 0b1, A2_tfrih>;
}
let isReMaterializable = 1, isMoveImm = 1, isAsmParserOnly = 1 in {
@@ -59,11 +71,13 @@ let isReMaterializable = 1, isMoveImm =
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
isCodeGenOnly = 1 in
-def PS_true : SInst<(outs PredRegs:$dst), (ins), "", []>;
+def PS_true : InstHexagon<(outs PredRegs:$dst), (ins), "",
+ [(set I1:$dst, 1)], "", C2_orn.Itinerary, TypeCR>;
let hasSideEffects = 0, isReMaterializable = 1, isPseudo = 1,
isCodeGenOnly = 1 in
-def PS_false : SInst<(outs PredRegs:$dst), (ins), "", []>;
+def PS_false : InstHexagon<(outs PredRegs:$dst), (ins), "",
+ [(set I1:$dst, 0)], "", C2_andn.Itinerary, TypeCR>;
let Defs = [R29, R30], Uses = [R31, R30, R29], isPseudo = 1 in
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
@@ -90,10 +104,10 @@ def ENDLOOP1 : Endloop<(outs), (ins b30_
let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
opExtendable = 0, hasSideEffects = 0 in
-class LOOP_iBase<string mnemonic, Operand brOp, bit mustExtend = 0>
- : CRInst<(outs), (ins brOp:$offset, u10_0Imm:$src2),
+class LOOP_iBase<string mnemonic, InstHexagon rootInst>
+ : InstHexagon <(outs), (ins b30_2Imm:$offset, u10_0Imm:$src2),
#mnemonic#"($offset,#$src2)",
- [], "" , CR_tc_3x_SLOT3> {
+ [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
bits<9> offset;
bits<10> src2;
@@ -110,10 +124,10 @@ class LOOP_iBase<string mnemonic, Operan
let isExtendable = 1, isExtentSigned = 1, opExtentBits = 9, opExtentAlign = 2,
opExtendable = 0, hasSideEffects = 0 in
-class LOOP_rBase<string mnemonic, Operand brOp, bit mustExtend = 0>
- : CRInst<(outs), (ins brOp:$offset, IntRegs:$src2),
+class LOOP_rBase<string mnemonic, InstHexagon rootInst>
+ : InstHexagon<(outs), (ins b30_2Imm:$offset, IntRegs:$src2),
#mnemonic#"($offset,$src2)",
- [], "" ,CR_tc_3x_SLOT3> {
+ [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
bits<9> offset;
bits<5> src2;
@@ -126,27 +140,25 @@ class LOOP_rBase<string mnemonic, Operan
let Inst{4-3} = offset{3-2};
}
-multiclass LOOP_ri<string mnemonic> {
- let isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
- def iext: LOOP_iBase<mnemonic, b30_2Imm, 1>;
- def rext: LOOP_rBase<mnemonic, b30_2Imm, 1>;
- }
+let Defs = [SA0, LC0, USR], isCodeGenOnly = 1, isExtended = 1,
+ opExtendable = 0 in {
+ def J2_loop0iext : LOOP_iBase<"loop0", J2_loop0i>;
+ def J2_loop1iext : LOOP_iBase<"loop1", J2_loop1i>;
}
-
-let Defs = [SA0, LC0, USR] in
-defm J2_loop0 : LOOP_ri<"loop0">;
-
// Interestingly only loop0's appear to set usr.lpcfg
-let Defs = [SA1, LC1] in
-defm J2_loop1 : LOOP_ri<"loop1">;
+let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
+ def J2_loop0rext : LOOP_rBase<"loop0", J2_loop0r>;
+ def J2_loop1rext : LOOP_rBase<"loop1", J2_loop1r>;
+}
let isCall = 1, hasSideEffects = 1, isPredicable = 0,
isExtended = 0, isExtendable = 1, opExtendable = 0,
isExtentSigned = 1, opExtentBits = 24, opExtentAlign = 2 in
class T_Call<string ExtStr>
- : JInst<(outs), (ins a30_2Imm:$dst),
- "call " # ExtStr # "$dst", [], "", J_tc_2early_SLOT23> {
+ : InstHexagon<(outs), (ins a30_2Imm:$dst),
+ "call " # ExtStr # "$dst", [], "", J2_call.Itinerary, TypeJ>,
+ OpcodeHexagon {
let BaseOpcode = "call";
bits<24> dst;
@@ -164,38 +176,24 @@ let isCodeGenOnly = 1, isCall = 1, hasSi
Defs = [PC, R31, R6, R7, P0] in
def PS_call_stk : T_Call<"">;
-let isCall = 1, hasSideEffects = 1, cofMax1 = 1 in
-class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
- dag InputDag = (ins IntRegs:$Rs)>
- : JInst<(outs), InputDag,
- !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
- "if ($Pu) callr $Rs"),
- "callr $Rs"),
- [], "", J_tc_2early_SLOT2> {
+// Call, no return.
+let isCall = 1, hasSideEffects = 1, cofMax1 = 1, isCodeGenOnly = 1 in
+def PS_callr_nr: InstHexagon<(outs), (ins IntRegs:$Rs),
+ "callr $Rs", [], "", J2_callr.Itinerary, TypeJ>, OpcodeHexagon {
bits<5> Rs;
bits<2> Pu;
- let isPredicated = isPred;
- let isPredicatedFalse = isPredNot;
+ let isPredicatedFalse = 1;
let IClass = 0b0101;
- let Inst{27-25} = 0b000;
- let Inst{24-23} = !if (isPred, 0b10, 0b01);
- let Inst{22} = 0;
- let Inst{21} = isPredNot;
- let Inst{9-8} = !if (isPred, Pu, 0b00);
+ let Inst{27-21} = 0b0000101;
let Inst{20-16} = Rs;
-
}
-let isCodeGenOnly = 1 in {
- def PS_callr_nr : JUMPR_MISC_CALLR<0, 1>; // Call, no return.
-}
-
let isCall = 1, hasSideEffects = 1,
isExtended = 0, isExtendable = 1, opExtendable = 0, isCodeGenOnly = 1,
- BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2,
- Itinerary = J_tc_2early_SLOT23 in
-class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops>
+ BaseOpcode = "PS_call_nr", isExtentSigned = 1, opExtentAlign = 2 in
+class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops,
+ InstrItinClass itin>
: Pseudo<(outs), iops, "">, PredRel {
bits<2> Pu;
bits<17> dst;
@@ -205,16 +203,18 @@ class Call_nr<bits<5> nbits, bit isPred,
let isPredicatedFalse = isFalse;
}
-def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii)>;
-//def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst)>;
-//def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst)>;
+def PS_call_nr : Call_nr<24, 0, 0, (ins s32_0Imm:$Ii), J2_call.Itinerary>;
+//def PS_call_nrt: Call_nr<17, 1, 0, (ins PredRegs:$Pu, s32_0Imm:$dst),
+// J2_callt.Itinerary>;
+//def PS_call_nrf: Call_nr<17, 1, 1, (ins PredRegs:$Pu, s32_0Imm:$dst),
+// J2_callf.Itinerary>;
let isBranch = 1, isIndirectBranch = 1, isBarrier = 1, Defs = [PC],
isPredicable = 1, hasSideEffects = 0, InputType = "reg",
cofMax1 = 1 in
-class T_JMPr
+class T_JMPr <InstHexagon rootInst>
: InstHexagon<(outs), (ins IntRegs:$dst), "jumpr $dst", [],
- "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon {
+ "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
bits<5> dst;
let IClass = 0b0101;
@@ -225,12 +225,12 @@ class T_JMPr
// A return through builtin_eh_return.
let isReturn = 1, isTerminator = 1, isBarrier = 1, hasSideEffects = 0,
isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
-def EH_RETURN_JMPR : T_JMPr;
+def EH_RETURN_JMPR : T_JMPr<J2_jumpr>;
// Indirect tail-call.
let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
isTerminator = 1, isCodeGenOnly = 1 in
-def PS_tailcall_r : T_JMPr;
+def PS_tailcall_r : T_JMPr<J2_jumpr>;
//
// Direct tail-calls.
@@ -262,11 +262,11 @@ class JumpOpcStr<string Mnemonic, bit Ne
}
let isBranch = 1, isIndirectBranch = 1, Defs = [PC], isPredicated = 1,
hasSideEffects = 0, InputType = "reg", cofMax1 = 1 in
-class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak>
+class T_JMPr_c <bit PredNot, bit isPredNew, bit isTak, InstHexagon rootInst>
: InstHexagon<(outs), (ins PredRegs:$src, IntRegs:$dst),
CondStr<"$src", !if(PredNot,0,1), isPredNew>.S #
JumpOpcStr<"jumpr", isPredNew, isTak>.S # " $dst",
- [], "", J_tc_2early_SLOT2, TypeJ>, OpcodeHexagon {
+ [], "", rootInst.Itinerary, rootInst.Type>, OpcodeHexagon {
let isTaken = isTak;
let isPredicatedFalse = PredNot;
@@ -283,30 +283,25 @@ class T_JMPr_c <bit PredNot, bit isPredN
let Inst{11} = isPredNew;
let Inst{9-8} = src;
}
-multiclass JMPR_Pred<bit PredNot> {
- def NAME : T_JMPr_c<PredNot, 0, 0>; // not taken
- // Predicate new
- def NAME#newpt : T_JMPr_c<PredNot, 1, 1>; // taken
- def NAME#new : T_JMPr_c<PredNot, 1, 0>; // not taken
-}
-multiclass JMPR_base<string BaseOp> {
- let BaseOpcode = BaseOp in {
- def NAME : T_JMPr;
- defm t : JMPR_Pred<0>;
- defm f : JMPR_Pred<1>;
- }
+
+let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1,
+ isBarrier = 1, BaseOpcode = "JMPret" in {
+ def PS_jmpret : T_JMPr<J2_jumpr>, PredNewRel;
+ def PS_jmprett : T_JMPr_c<0, 0, 0, J2_jumprt>, PredNewRel;
+ def PS_jmpretf : T_JMPr_c<1, 0, 0, J2_jumprf>, PredNewRel;
+ def PS_jmprettnew : T_JMPr_c<0, 1, 0, J2_jumprtnew>, PredNewRel;
+ def PS_jmpretfnew : T_JMPr_c<1, 1, 0, J2_jumprfnew>, PredNewRel;
+ def PS_jmprettnewpt : T_JMPr_c<0, 1, 1, J2_jumprtnewpt>, PredNewRel;
+ def PS_jmpretfnewpt : T_JMPr_c<1, 1, 1, J2_jumprfnewpt>, PredNewRel;
}
-let isTerminator = 1, hasSideEffects = 0, isReturn = 1, isCodeGenOnly = 1, isBarrier = 1 in
-defm PS_jmpret : JMPR_base<"JMPret">, PredNewRel;
//defm V6_vtran2x2_map : HexagonMapping<(outs VectorRegs:$Vy32, VectorRegs:$Vx32), (ins VectorRegs:$Vx32in, IntRegs:$Rt32), "vtrans2x2(${Vy32},${Vx32},${Rt32})", (V6_vshuff VectorRegs:$Vy32, VectorRegs:$Vx32, VectorRegs:$Vx32in, IntRegs:$Rt32)>;
// The reason for the custom inserter is to record all ALLOCA instructions
// in MachineFunctionInfo.
-let Defs = [R29], isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 1 in
-def PS_alloca: InstHexagon<(outs IntRegs:$Rd),
- (ins IntRegs:$Rs, u32_0Imm:$A), "",
- [], "", ALU32_2op_tc_1_SLOT0123, TypeALU32_2op>;
+let Defs = [R29], hasSideEffects = 1 in
+def PS_alloca: Pseudo <(outs IntRegs:$Rd),
+ (ins IntRegs:$Rs, u32_0Imm:$A), "", []>;
// Load predicate.
let isExtendable = 1, opExtendable = 2, isExtentSigned = 1, opExtentBits = 13,
@@ -322,35 +317,19 @@ def LDriw_mod : LDInst<(outs ModRegs:$ds
(ins IntRegs:$addr, s32_0Imm:$off),
".error \"should not emit\"", []>;
-// Vector load
-let Predicates = [HasV60T, UseHVX] in
-let mayLoad = 1, hasSideEffects = 0 in
- class V6_LDInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = CVI_VM_LD,
- IType type = TypeCVI_VM_LD>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
-
-// Vector store
-let Predicates = [HasV60T, UseHVX] in
-let mayStore = 1, hasSideEffects = 0 in
-class V6_STInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = CVI_VM_ST,
- IType type = TypeCVI_VM_ST>
-: InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
let isCodeGenOnly = 1, isPseudo = 1 in
-def PS_pselect : ALU64_rr<(outs DoubleRegs:$Rd),
+def PS_pselect: InstHexagon<(outs DoubleRegs:$Rd),
(ins PredRegs:$Pu, DoubleRegs:$Rs, DoubleRegs:$Rt),
- ".error \"should not emit\" ", []>;
+ ".error \"should not emit\" ", [], "", A2_tfrpt.Itinerary, TypeALU32_2op>;
let isBranch = 1, isBarrier = 1, Defs = [PC], hasSideEffects = 0,
isPredicable = 1,
isExtendable = 1, opExtendable = 0, isExtentSigned = 1,
opExtentBits = 24, opExtentAlign = 2, InputType = "imm" in
-class T_JMP<string ExtStr>
- : JInst_CJUMP_UCJUMP<(outs), (ins b30_2Imm:$dst),
- "jump " # ExtStr # "$dst",
- [], "", J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT> {
+class T_JMP: InstHexagon<(outs), (ins b30_2Imm:$dst),
+ "jump $dst",
+ [], "", J2_jump.Itinerary, TypeJ>, OpcodeHexagon {
bits<24> dst;
let IClass = 0b0101;
@@ -362,16 +341,16 @@ class T_JMP<string ExtStr>
// Restore registers and dealloc return function call.
let isCall = 1, isBarrier = 1, isReturn = 1, isTerminator = 1,
Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
- def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP<"">;
+ def RESTORE_DEALLOC_RET_JMP_V4 : T_JMP;
let isExtended = 1, opExtendable = 0 in
- def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP<"">;
+ def RESTORE_DEALLOC_RET_JMP_V4_EXT : T_JMP;
let Defs = [R14, R15, R28, R29, R30, R31, PC] in {
- def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP<"">;
+ def RESTORE_DEALLOC_RET_JMP_V4_PIC : T_JMP;
let isExtended = 1, opExtendable = 0 in
- def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP<"">;
+ def RESTORE_DEALLOC_RET_JMP_V4_EXT_PIC : T_JMP;
}
}
@@ -416,33 +395,38 @@ let isCall = 1, Uses = [R29, R31], isAsm
def SAVE_REGISTERS_CALL_V4STK_EXT_PIC : T_Call<"">, PredRel;
}
-// Vector load/store pseudos
+// Vector store pseudos
+let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
+ mayStore = 1, hasSideEffects = 0 in
+class STrivv_template<RegisterClass RC, InstHexagon rootInst>
+ : InstHexagon<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src),
+ "", [], "", rootInst.Itinerary, rootInst.Type>;
-let isPseudo = 1, isCodeGenOnly = 1 in
-class STrivv_template<RegisterClass RC>
- : V6_STInst<(outs), (ins IntRegs:$addr, s32_0Imm:$off, RC:$src), "", []>;
-
-def PS_vstorerw_ai: STrivv_template<VecDblRegs>,
- Requires<[HasV60T,UseHVXSgl]>;
-def PS_vstorerwu_ai: STrivv_template<VecDblRegs>,
+def PS_vstorerw_ai: STrivv_template<VecDblRegs, V6_vS32b_ai>,
Requires<[HasV60T,UseHVXSgl]>;
-def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B>,
- Requires<[HasV60T,UseHVXDbl]>;
-def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B>,
+def PS_vstorerw_ai_128B: STrivv_template<VecDblRegs128B, V6_vS32b_ai_128B>,
Requires<[HasV60T,UseHVXDbl]>;
+def PS_vstorerwu_ai: STrivv_template<VecDblRegs, V6_vS32Ub_ai>,
+ Requires<[HasV60T,UseHVXSgl]>;
+def PS_vstorerwu_ai_128B: STrivv_template<VecDblRegs128B, V6_vS32Ub_ai_128B>,
+ Requires<[HasV60T,UseHVXDbl]>;
-let isPseudo = 1, isCodeGenOnly = 1 in
-class LDrivv_template<RegisterClass RC>
- : V6_LDInst<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off), "", []>;
+// Vector load pseudos
+let Predicates = [HasV60T, UseHVX], isPseudo = 1, isCodeGenOnly = 1,
+ mayLoad = 1, hasSideEffects = 0 in
+class LDrivv_template<RegisterClass RC, InstHexagon rootInst>
+ : InstHexagon<(outs RC:$dst), (ins IntRegs:$addr, s32_0Imm:$off),
+ "", [], "", rootInst.Itinerary, rootInst.Type>;
-def PS_vloadrw_ai: LDrivv_template<VecDblRegs>,
+def PS_vloadrw_ai: LDrivv_template<VecDblRegs, V6_vL32b_ai>,
Requires<[HasV60T,UseHVXSgl]>;
-def PS_vloadrwu_ai: LDrivv_template<VecDblRegs>,
- Requires<[HasV60T,UseHVXSgl]>;
-def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B>,
+def PS_vloadrw_ai_128B: LDrivv_template<VecDblRegs128B, V6_vL32b_ai_128B>,
Requires<[HasV60T,UseHVXDbl]>;
-def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B>,
+
+def PS_vloadrwu_ai: LDrivv_template<VecDblRegs, V6_vL32Ub_ai>,
+ Requires<[HasV60T,UseHVXSgl]>;
+def PS_vloadrwu_ai_128B: LDrivv_template<VecDblRegs128B, V6_vL32Ub_ai_128B>,
Requires<[HasV60T,UseHVXDbl]>;
// Store vector predicate pseudo.
@@ -469,25 +453,23 @@ let isExtendable = 1, opExtendable = 1,
Requires<[HasV60T,UseHVXDbl]>;
}
-class VSELInst<dag outs, dag ins, string asmstr, list<dag> pattern = [],
- string cstr = "", InstrItinClass itin = CVI_VA_DV,
- IType type = TypeCVI_VA_DV>
- : InstHexagon<outs, ins, asmstr, pattern, cstr, itin, type>;
-
-let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in {
- def PS_vselect: VSELInst<(outs VectorRegs:$dst),
- (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3), "", []>,
- Requires<[HasV60T,UseHVXSgl]>;
- def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
- (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
- "", []>, Requires<[HasV60T,UseHVXDbl]>;
- def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
- (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3), "", []>,
- Requires<[HasV60T,UseHVXSgl]>;
- def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
- (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
- "", []>, Requires<[HasV60T,UseHVXDbl]>;
-}
+let isCodeGenOnly = 1, isPseudo = 1, hasSideEffects = 0 in
+class VSELInst<dag outs, dag ins, InstHexagon rootInst>
+ : InstHexagon<outs, ins, "", [], "", rootInst.Itinerary, rootInst.Type>;
+
+def PS_vselect: VSELInst<(outs VectorRegs:$dst),
+ (ins PredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
+ V6_vcmov>, Requires<[HasV60T,UseHVXSgl]>;
+def PS_vselect_128B: VSELInst<(outs VectorRegs128B:$dst),
+ (ins PredRegs:$src1, VectorRegs128B:$src2, VectorRegs128B:$src3),
+ V6_vcmov>, Requires<[HasV60T,UseHVXDbl]>;
+
+def PS_wselect: VSELInst<(outs VecDblRegs:$dst),
+ (ins PredRegs:$src1, VecDblRegs:$src2, VecDblRegs:$src3),
+ V6_vccombine>, Requires<[HasV60T,UseHVXSgl]>;
+def PS_wselect_128B: VSELInst<(outs VecDblRegs128B:$dst),
+ (ins PredRegs:$src1, VecDblRegs128B:$src2, VecDblRegs128B:$src3),
+ V6_vccombine>, Requires<[HasV60T,UseHVXDbl]>;
// Store predicate.
let isExtendable = 1, opExtendable = 1, isExtentSigned = 1, opExtentBits = 13,
@@ -504,8 +486,10 @@ def STriw_mod : STInst<(outs),
let isExtendable = 1, opExtendable = 1, opExtentBits = 6,
isAsmParserOnly = 1 in
-def TFRI64_V4 : ALU64_rr<(outs DoubleRegs:$dst), (ins u64_0Imm:$src1),
- "$dst = #$src1">;
+def TFRI64_V4 : InstHexagon<(outs DoubleRegs:$dst),
+ (ins u64_0Imm:$src1),
+ "$dst = #$src1", [], "",
+ A2_combineii.Itinerary, TypeALU32_2op>, OpcodeHexagon;
// Hexagon doesn't have a vector multiply with C semantics.
// Instead, generate a pseudo instruction that gets expaneded into two
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSchedule.td Wed May 3 15:10:36 2017
@@ -7,6 +7,55 @@
//
//===----------------------------------------------------------------------===//
+def Hex_FWD : Bypass;
+def HVX_FWD : Bypass;
+
+// Functional Units.
+def SLOT0 : FuncUnit;
+def SLOT1 : FuncUnit;
+def SLOT2 : FuncUnit;
+def SLOT3 : FuncUnit;
+// Endloop is a pseudo instruction that is encoded with 2 bits in a packet
+// rather than taking an execution slot. This special unit is needed
+// to schedule an ENDLOOP with 4 other instructions.
+def SLOT_ENDLOOP: FuncUnit;
+
+// CVI pipes from the "Hexagon Multimedia Co-Processor Extensions Arch Spec".
+def CVI_ST : FuncUnit;
+def CVI_XLANE : FuncUnit;
+def CVI_SHIFT : FuncUnit;
+def CVI_MPY0 : FuncUnit;
+def CVI_MPY1 : FuncUnit;
+def CVI_LD : FuncUnit;
+
+// Combined functional units.
+def CVI_XLSHF : FuncUnit;
+def CVI_MPY01 : FuncUnit;
+def CVI_ALL : FuncUnit;
+def CVI_ALL_NOMEM : FuncUnit;
+
+// Combined functional unit data.
+def HexagonComboFuncsV60 :
+ ComboFuncUnits<[
+ ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>,
+ ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>,
+ ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT,
+ CVI_MPY0, CVI_MPY1, CVI_LD]>,
+ ComboFuncData<CVI_ALL_NOMEM, [CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1]>
+ ]>;
+
+// Itinerary classes.
+def PSEUDO : InstrItinClass;
+def PSEUDOM : InstrItinClass;
+def DUPLEX : InstrItinClass;
+def tc_ENDLOOP : InstrItinClass;
+
+//===----------------------------------------------------------------------===//
+// Auto-generated itinerary classes
+//===----------------------------------------------------------------------===//
+include "HexagonDepIICScalar.td"
+include "HexagonDepIICHVX.td"
+
//===----------------------------------------------------------------------===//
// V4 Machine Info +
//===----------------------------------------------------------------------===//
@@ -20,9 +69,9 @@ include "HexagonScheduleV55.td"
// V60 Machine Info -
//===----------------------------------------------------------------------===//
-include "HexagonScheduleV60.td"
include "HexagonIICScalar.td"
include "HexagonIICHVX.td"
+include "HexagonScheduleV60.td"
//===----------------------------------------------------------------------===//
// V62 Machine Info +
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV4.td Wed May 3 15:10:36 2017
@@ -7,200 +7,31 @@
//
//===----------------------------------------------------------------------===//
-// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
-// This file describes that machine information.
+def LD_tc_ld_SLOT01 : InstrItinClass;
+def ST_tc_st_SLOT01 : InstrItinClass;
-//
-// |===========|==================================================|
-// | PIPELINE | Instruction Classes |
-// |===========|==================================================|
-// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
-// |-----------|--------------------------------------------------|
-// | SLOT1 | LD ST ALU32 |
-// |-----------|--------------------------------------------------|
-// | SLOT2 | XTYPE ALU32 J JR |
-// |-----------|--------------------------------------------------|
-// | SLOT3 | XTYPE ALU32 J CR |
-// |===========|==================================================|
-
-// Functional Units.
-def SLOT0 : FuncUnit;
-def SLOT1 : FuncUnit;
-def SLOT2 : FuncUnit;
-def SLOT3 : FuncUnit;
-// Endloop is a pseudo instruction that is encoded with 2 bits in a packet
-// rather than taking an execution slot. This special unit is needed
-// to schedule an ENDLOOP with 4 other instructions.
-def SLOT_ENDLOOP: FuncUnit;
-
-// Itinerary classes.
-def PSEUDO : InstrItinClass;
-def PSEUDOM : InstrItinClass;
-// ALU64/M/S Instruction classes of V2 are collectively knownn as XTYPE in V4.
-def DUPLEX : InstrItinClass;
-def PREFIX : InstrItinClass;
-def COMPOUND_CJ_ARCHDEPSLOT : InstrItinClass;
-def COMPOUND : InstrItinClass;
-
-def ALU32_2op_tc_1_SLOT0123 : InstrItinClass;
-def ALU32_2op_tc_2early_SLOT0123 : InstrItinClass;
-def ALU32_3op_tc_2early_SLOT0123 : InstrItinClass;
-def ALU32_3op_tc_1_SLOT0123 : InstrItinClass;
-def ALU32_3op_tc_2_SLOT0123 : InstrItinClass;
-def ALU32_ADDI_tc_1_SLOT0123 : InstrItinClass;
-def ALU64_tc_1_SLOT23 : InstrItinClass;
-def ALU64_tc_2_SLOT23 : InstrItinClass;
-def ALU64_tc_2early_SLOT23 : InstrItinClass;
-def ALU64_tc_3x_SLOT23 : InstrItinClass;
-def CR_tc_2_SLOT3 : InstrItinClass;
-def CR_tc_2early_SLOT23 : InstrItinClass;
-def CR_tc_2early_SLOT3 : InstrItinClass;
-def CR_tc_3x_SLOT23 : InstrItinClass;
-def CR_tc_3x_SLOT3 : InstrItinClass;
-def J_tc_2early_SLOT23 : InstrItinClass;
-def J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT : InstrItinClass;
-def J_tc_2early_SLOT2 : InstrItinClass;
-def LD_tc_ld_SLOT01 : InstrItinClass;
-def LD_tc_ld_pi_SLOT01 : InstrItinClass;
-def LD_tc_ld_SLOT0 : InstrItinClass;
-def LD_tc_3or4stall_SLOT0 : InstrItinClass;
-def M_tc_2_SLOT23 : InstrItinClass;
-def M_tc_2_acc_SLOT23 : InstrItinClass;
-def M_tc_3_SLOT23 : InstrItinClass;
-def M_tc_1_SLOT23 : InstrItinClass;
-def M_tc_3x_SLOT23 : InstrItinClass;
-def M_tc_3x_acc_SLOT23 : InstrItinClass;
-def M_tc_3or4x_SLOT23 : InstrItinClass;
-def M_tc_3or4x_acc_SLOT23 : InstrItinClass;
-def ST_tc_st_SLOT01 : InstrItinClass;
-def ST_tc_st_pi_SLOT01 : InstrItinClass;
-def ST_tc_st_SLOT0 : InstrItinClass;
-def ST_tc_st_pi_SLOT0 : InstrItinClass;
-def ST_tc_ld_SLOT0 : InstrItinClass;
-def ST_tc_3stall_SLOT0 : InstrItinClass;
-def S_2op_tc_1_SLOT23 : InstrItinClass;
-def S_2op_tc_2_SLOT23 : InstrItinClass;
-def S_2op_tc_2early_SLOT23 : InstrItinClass;
-def S_2op_tc_3or4x_SLOT23 : InstrItinClass;
-def S_3op_tc_1_SLOT23 : InstrItinClass;
-def S_3op_tc_2_SLOT23 : InstrItinClass;
-def S_3op_tc_2early_SLOT23 : InstrItinClass;
-def S_3op_tc_3_SLOT23 : InstrItinClass;
-def S_3op_tc_3x_SLOT23 : InstrItinClass;
-def NCJ_tc_3or4stall_SLOT0 : InstrItinClass;
-def V2LDST_tc_ld_SLOT01 : InstrItinClass;
-def V2LDST_tc_st_SLOT0 : InstrItinClass;
-def V2LDST_tc_st_SLOT01 : InstrItinClass;
-def V4LDST_tc_ld_SLOT01 : InstrItinClass;
-def V4LDST_tc_st_SLOT0 : InstrItinClass;
-def V4LDST_tc_st_SLOT01 : InstrItinClass;
-def J_tc_2early_SLOT0123 : InstrItinClass;
-def EXTENDER_tc_1_SLOT0123 : InstrItinClass;
-def S_3op_tc_3stall_SLOT23 : InstrItinClass;
+class HexagonV4PseudoItin {
+ list<InstrItinData> V4PseudoItin_list = [
+ InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
+ InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [SLOT2, SLOT3]>]>,
+ InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>]>,
+ InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>]>
+ ];
+}
+
+def HexagonV4ItinList : DepScalarItinV4, HexagonV4PseudoItin {
+ list<InstrItinData> V4Itin_list = [
+ InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
+ InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>
+ ];
+ list<InstrItinData> ItinList =
+ !listconcat(V4Itin_list, DepScalarItinV4_list, V4PseudoItin_list);
+}
def HexagonItinerariesV4 :
- ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
- // ALU32
- InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_2op_tc_2early_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_3op_tc_2early_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-
- // ALU64
- InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<ALU64_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
-
- // CR -> System
- InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>]>,
- InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>]>,
- InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>]>,
-
- // Jump (conditional/unconditional/return etc)
- // CR
- InstrItinData<CR_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- // J
- InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
- // JR
- InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>]>,
-
- //Load
- InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<LD_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
-
- // M
- InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
-
- // Store
- // ST
- InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<ST_tc_st_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- // ST0
- InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>]>,
-
- // S
- InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_2op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_3stall_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
-
- // SYS
- InstrItinData<ST_tc_3stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
-
- // New Value Compare Jump
- InstrItinData<NCJ_tc_3or4stall_SLOT0 , [InstrStage<1, [SLOT0]>]>,
-
- // Mem ops - MEM_V4
- InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
-
- InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
-
- // ENDLOOP
- InstrItinData<J_tc_2early_SLOT0123 , [InstrStage<1, [SLOT_ENDLOOP]>]>,
-
- // Extender/PREFIX
- InstrItinData<EXTENDER_tc_1_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-
- InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [SLOT2, SLOT3]>]>
- ]>;
+ ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
+ [Hex_FWD], HexagonV4ItinList.ItinList>;
def HexagonModelV4 : SchedMachineModel {
// Max issue per cycle == bundle width.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV55.td Wed May 3 15:10:36 2017
@@ -1,4 +1,4 @@
-//=-HexagonScheduleV4.td - HexagonV4 Scheduling Definitions --*- tablegen -*-=//
+//=-HexagonScheduleV55.td - HexagonV55 Scheduling Definitions -*- tablegen -*=//
//
// The LLVM Compiler Infrastructure
//
@@ -7,190 +7,33 @@
//
//===----------------------------------------------------------------------===//
-// There are four SLOTS (four parallel pipelines) in Hexagon V4 machine.
-// This file describes that machine information.
-//
-// |===========|==================================================|
-// | PIPELINE | Instruction Classes |
-// |===========|==================================================|
-// | SLOT0 | LD ST ALU32 MEMOP NV SYSTEM |
-// |-----------|--------------------------------------------------|
-// | SLOT1 | LD ST ALU32 |
-// |-----------|--------------------------------------------------|
-// | SLOT2 | XTYPE ALU32 J JR |
-// |-----------|--------------------------------------------------|
-// | SLOT3 | XTYPE ALU32 J CR |
-// |===========|==================================================|
-
-def CJ_tc_1_SLOT23 : InstrItinClass;
-def CJ_tc_2early_SLOT23 : InstrItinClass;
-def COPROC_VMEM_vtc_long_SLOT01 : InstrItinClass;
-def COPROC_VX_vtc_long_SLOT23 : InstrItinClass;
-def COPROC_VX_vtc_SLOT23 : InstrItinClass;
-def J_tc_3stall_SLOT2 : InstrItinClass;
-def MAPPING_tc_1_SLOT0123 : InstrItinClass;
-def M_tc_3stall_SLOT23 : InstrItinClass;
+class HexagonV55PseudoItin {
+ list<InstrItinData> V55PseudoItin_list = [
+ InstrItinData<PSEUDO, [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
+ [1, 1, 1]>,
+ InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
+ InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>,
+ InstrItinData<DUPLEX, [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
+ InstrItinData<tc_ENDLOOP, [InstrStage<1, [SLOT_ENDLOOP]>], [2]>
+ ];
+}
+
+def HexagonV55ItinList : DepScalarItinV55,
+ HexagonV55PseudoItin {
+ list<InstrItinData> V55Itin_list = [
+ InstrItinData<LD_tc_ld_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>], [2, 1]>,
+ InstrItinData<ST_tc_st_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
+ [1, 1, 1]>
+ ];
+ list<InstrItinData> ItinList =
+ !listconcat(V55Itin_list, DepScalarItinV55_list,
+ V55PseudoItin_list);
+}
def HexagonItinerariesV55 :
- ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP], [], [
- // ALU32
- InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
- InstrItinData<ALU32_2op_tc_2early_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
- InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
- InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
- InstrItinData<ALU32_3op_tc_2early_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [2, 1, 1]>,
- InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
-
- // ALU64
- InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
-
- // CR -> System
- InstrItinData<CR_tc_2_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
- InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<1, [SLOT3]>], [2, 1, 1]>,
- InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<1, [SLOT3]>], [3, 1, 1]>,
-
- // Jump (conditional/unconditional/return etc)
- InstrItinData<CR_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1, 1]>,
- InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1, 1]>,
- InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1, 1]>,
- InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1, 1]>,
- InstrItinData<J_tc_2early_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1, 1]>,
- InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT,
- [InstrStage<1, [SLOT2, SLOT3]>], [2, 1, 1, 1]>,
-
- // JR
- InstrItinData<J_tc_2early_SLOT2 , [InstrStage<1, [SLOT2]>], [2, 1, 1]>,
- InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<1, [SLOT2]>], [3, 1, 1]>,
-
- // Extender
- InstrItinData<EXTENDER_tc_1_SLOT0123,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>], [1, 1, 1]>,
-
- // Load
- InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [2, 1]>,
- InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [2, 1]>,
- InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1]>,
- InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1]>,
-
- // M
- InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<M_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<M_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<M_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1, 1]>,
- InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<M_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
-
- // Store
- InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1]>,
- InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1]>,
- InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
- InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<1, [SLOT0]>], [2, 1, 1]>,
- InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
- InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
-
- // S
- InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [2, 1, 1]>,
- InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
- InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>],
- [3, 1, 1]>,
-
- // New Value Compare Jump
- InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<1, [SLOT0]>],
- [3, 1, 1, 1]>,
-
- // Mem ops
- InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
- [1, 1, 1, 1]>,
- InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [2, 1, 1, 1]>,
- InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1, 1]>,
- InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>],
- [1, 1, 1, 1]>,
- InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [3, 1, 1, 1]>,
- InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>],
- [1, 1, 1, 1]>,
-
- // Endloop
- InstrItinData<J_tc_2early_SLOT0123, [InstrStage<1, [SLOT_ENDLOOP]>],
- [2]>,
-
- // Vector
- InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
- [InstrStage<1, [SLOT0, SLOT1]>], [2, 1, 1, 1]>,
- InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>,
- InstrItinData<COPROC_VX_vtc_SLOT23 ,
- [InstrStage<1, [SLOT2, SLOT3]>], [3, 1, 1, 1]>,
- InstrItinData<MAPPING_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
- [1, 1, 1, 1]>,
-
- // Misc
- InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>], [1, 1, 1]>,
- InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>],
- [1, 1, 1]>,
- InstrItinData<PSEUDOM, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [SLOT2, SLOT3]>], [1, 1, 1]>
- ]>;
+ ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP],
+ [Hex_FWD], HexagonV55ItinList.ItinList>;
def HexagonModelV55 : SchedMachineModel {
// Max issue per cycle == bundle width.
@@ -201,5 +44,5 @@ def HexagonModelV55 : SchedMachineModel
}
//===----------------------------------------------------------------------===//
-// Hexagon V4 Resource Definitions -
+// Hexagon V55 Resource Definitions -
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV60.td Wed May 3 15:10:36 2017
@@ -7,61 +7,6 @@
//
//===----------------------------------------------------------------------===//
-// CVI pipes from the "Hexagon Multimedia Co-Processor Extensions Arch Spec".
-def CVI_ST : FuncUnit;
-def CVI_XLANE : FuncUnit;
-def CVI_SHIFT : FuncUnit;
-def CVI_MPY0 : FuncUnit;
-def CVI_MPY1 : FuncUnit;
-def CVI_LD : FuncUnit;
-
-// Combined functional units.
-def CVI_XLSHF : FuncUnit;
-def CVI_MPY01 : FuncUnit;
-def CVI_ALL : FuncUnit;
-def CVI_XLMPY0 : FuncUnit;
-def CVI_SHFMPY1: FuncUnit;
-
-// Combined functional unit data.
-def HexagonComboFuncsV60 :
- ComboFuncUnits<[
- ComboFuncData<CVI_XLSHF , [CVI_XLANE, CVI_SHIFT]>,
- ComboFuncData<CVI_MPY01 , [CVI_MPY0, CVI_MPY1]>,
- ComboFuncData<CVI_ALL , [CVI_ST, CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1, CVI_LD]>,
- ComboFuncData<CVI_XLMPY0 , [CVI_XLANE, CVI_MPY0]>,
- ComboFuncData<CVI_SHFMPY1 , [CVI_SHIFT, CVI_MPY1]>
- ]>;
-
-// Note: When adding additional vector scheduling classes, add the
-// corresponding methods to the class HexagonInstrInfo.
-def CVI_VA : InstrItinClass;
-def CVI_VA_DV : InstrItinClass;
-def CVI_VX_LONG : InstrItinClass;
-def CVI_VX_LATE : InstrItinClass;
-def CVI_VX : InstrItinClass;
-def CVI_VX_DV_LONG : InstrItinClass;
-def CVI_VX_DV : InstrItinClass;
-def CVI_VX_DV_SLOT2 : InstrItinClass;
-def CVI_VX_DV_SLOT2_LONG_EARLY : InstrItinClass;
-def CVI_VP : InstrItinClass;
-def CVI_VP_LONG : InstrItinClass;
-def CVI_VP_VS_EARLY : InstrItinClass;
-def CVI_VP_VS_LONG_EARLY : InstrItinClass;
-def CVI_VP_VS_LONG : InstrItinClass;
-def CVI_VP_VS : InstrItinClass;
-def CVI_VP_DV : InstrItinClass;
-def CVI_VS : InstrItinClass;
-def CVI_VINLANESAT : InstrItinClass;
-def CVI_VM_LD : InstrItinClass;
-def CVI_VM_TMP_LD : InstrItinClass;
-def CVI_VM_CUR_LD : InstrItinClass;
-def CVI_VM_VP_LDU : InstrItinClass;
-def CVI_VM_ST : InstrItinClass;
-def CVI_VM_NEW_ST : InstrItinClass;
-def CVI_VM_STU : InstrItinClass;
-def CVI_HIST : InstrItinClass;
-def CVI_VA_EXT : InstrItinClass;
// There are four SLOTS (four parallel pipelines) in Hexagon V60 machine.
// This file describes that machine information.
@@ -108,196 +53,20 @@ def CVI_VA_EXT : InstrItinClass;
// S0123| CVI_VA_EXT Extract |
// |=====================================================================|
+def HexagonV60ItinList : DepScalarItinV60, ScalarItin,
+ DepHVXItinV60,
+ HVXItin, PseudoItin {
+ list<InstrItinData> ItinList =
+ !listconcat(DepScalarItinV60_list, ScalarItin_list,
+ DepHVXItinV60_list, HVXItin_list, PseudoItin_list);
+}
+
def HexagonItinerariesV60 :
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
- CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL], [], [
- // ALU32
- InstrItinData<ALU32_2op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_2op_tc_2early_SLOT0123,
- [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_3op_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_3op_tc_2_SLOT0123 ,
- [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_3op_tc_2early_SLOT0123,
- [InstrStage<2, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<ALU32_ADDI_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-
- // ALU64
- InstrItinData<ALU64_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<ALU64_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<ALU64_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<ALU64_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
-
- // CR -> System
- InstrItinData<CR_tc_2_SLOT3 , [InstrStage<2, [SLOT3]>]>,
- InstrItinData<CR_tc_2early_SLOT3 , [InstrStage<2, [SLOT3]>]>,
- InstrItinData<CR_tc_3x_SLOT3 , [InstrStage<3, [SLOT3]>]>,
-
- // Jump (conditional/unconditional/return etc)
- InstrItinData<CR_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<CR_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<CJ_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<CJ_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<J_tc_2early_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<J_tc_2early_CJUMP_UCJUMP_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
-
- // JR
- InstrItinData<J_tc_2early_SLOT2 , [InstrStage<2, [SLOT2]>]>,
- InstrItinData<J_tc_3stall_SLOT2 , [InstrStage<3, [SLOT2]>]>,
-
- // Extender
- InstrItinData<EXTENDER_tc_1_SLOT0123, [InstrStage<1,
- [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-
- // Load
- InstrItinData<LD_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
- InstrItinData<LD_tc_ld_pi_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
- InstrItinData<LD_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
- InstrItinData<LD_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
-
- // M
- InstrItinData<M_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_2_acc_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3x_acc_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3or4x_acc_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
- InstrItinData<M_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
-
- // Store
- InstrItinData<ST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<ST_tc_st_pi_SLOT01, [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<ST_tc_3stall_SLOT0, [InstrStage<3, [SLOT0]>]>,
- InstrItinData<ST_tc_ld_SLOT0 , [InstrStage<3, [SLOT0]>]>,
- InstrItinData<ST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<ST_tc_st_pi_SLOT0 , [InstrStage<1, [SLOT0]>]>,
-
- // S
- InstrItinData<S_2op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_2op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<S_2op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
- // The S_2op_tc_3x_SLOT23 slots are 4 cycles on v60.
- InstrItinData<S_2op_tc_3or4x_SLOT23 , [InstrStage<4, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_1_SLOT23 , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_2_SLOT23 , [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_2early_SLOT23, [InstrStage<2, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_3_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_3stall_SLOT23, [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<S_3op_tc_3x_SLOT23 , [InstrStage<3, [SLOT2, SLOT3]>]>,
-
- // New Value Compare Jump
- InstrItinData<NCJ_tc_3or4stall_SLOT0, [InstrStage<4, [SLOT0]>]>,
-
- // Mem ops
- InstrItinData<V2LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<V2LDST_tc_ld_SLOT01 , [InstrStage<2, [SLOT0, SLOT1]>]>,
- InstrItinData<V2LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
- InstrItinData<V4LDST_tc_st_SLOT0 , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<V4LDST_tc_ld_SLOT01 , [InstrStage<3, [SLOT0, SLOT1]>]>,
- InstrItinData<V4LDST_tc_st_SLOT01 , [InstrStage<1, [SLOT0, SLOT1]>]>,
-
- // Endloop
- InstrItinData<J_tc_2early_SLOT0123, [InstrStage<2, [SLOT_ENDLOOP]>]>,
-
- // Vector
- InstrItinData<COPROC_VMEM_vtc_long_SLOT01,
- [InstrStage<3, [SLOT0, SLOT1]>]>,
- InstrItinData<COPROC_VX_vtc_long_SLOT23 ,
- [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<COPROC_VX_vtc_SLOT23 ,
- [InstrStage<3, [SLOT2, SLOT3]>]>,
- InstrItinData<MAPPING_tc_1_SLOT0123 ,
- [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
-
- // Duplex and Compound
- InstrItinData<DUPLEX , [InstrStage<1, [SLOT0]>]>,
- InstrItinData<COMPOUND_CJ_ARCHDEPSLOT , [InstrStage<1, [SLOT2, SLOT3]>]>,
- InstrItinData<COMPOUND , [InstrStage<1, [SLOT2, SLOT3]>]>,
- // Misc
- InstrItinData<PREFIX , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<PSEUDO , [InstrStage<1, [SLOT0, SLOT1, SLOT2, SLOT3]>]>,
- InstrItinData<PSEUDOM , [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [SLOT2, SLOT3]>]>,
-
- // Latest CVI spec definitions.
- InstrItinData<CVI_VA,[InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLANE,CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>]>,
- InstrItinData<CVI_VA_DV,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF, CVI_MPY01]>]>,
- InstrItinData<CVI_VX_LONG, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
- InstrItinData<CVI_VX_LATE, [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
- InstrItinData<CVI_VX,[InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY0, CVI_MPY1]>]>,
- InstrItinData<CVI_VX_DV_LONG,
- [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY01]>]>,
- InstrItinData<CVI_VX_DV,
- [InstrStage<1, [SLOT2, SLOT3], 0>,
- InstrStage<1, [CVI_MPY01]>]>,
- InstrItinData<CVI_VX_DV_SLOT2,
- [InstrStage<1, [SLOT2], 0>,
- InstrStage<1, [CVI_MPY01]>]>,
- InstrItinData<CVI_VP, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLANE]>]>,
- InstrItinData<CVI_VP_LONG, [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLANE]>]>,
- InstrItinData<CVI_VP_VS_EARLY,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>]>,
- InstrItinData<CVI_VP_VS_LONG,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>]>,
- InstrItinData<CVI_VP_VS,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>]>,
- InstrItinData<CVI_VP_VS_LONG_EARLY,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>]>,
- InstrItinData<CVI_VP_DV , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_XLSHF]>]>,
- InstrItinData<CVI_VS,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_SHIFT]>]>,
- InstrItinData<CVI_VINLANESAT,
- [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_SHIFT]>]>,
- InstrItinData<CVI_VM_LD , [InstrStage<1, [SLOT0, SLOT1], 0>,
- InstrStage<1, [CVI_LD], 0>,
- InstrStage<1, [CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>]>,
- InstrItinData<CVI_VM_TMP_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
- InstrStage<1, [CVI_LD]>]>,
- InstrItinData<CVI_VM_CUR_LD,[InstrStage<1,[SLOT0, SLOT1], 0>,
- InstrStage<1, [CVI_LD], 0>,
- InstrStage<1, [CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>]>,
- InstrItinData<CVI_VM_VP_LDU,[InstrStage<1,[SLOT0], 0>,
- InstrStage<1, [SLOT1], 0>,
- InstrStage<1, [CVI_LD], 0>,
- InstrStage<1, [CVI_XLANE]>]>,
- InstrItinData<CVI_VM_ST , [InstrStage<1, [SLOT0], 0>,
- InstrStage<1, [CVI_ST], 0>,
- InstrStage<1, [CVI_XLANE, CVI_SHIFT,
- CVI_MPY0, CVI_MPY1]>]>,
- InstrItinData<CVI_VM_NEW_ST,[InstrStage<1,[SLOT0], 0>,
- InstrStage<1, [CVI_ST]>]>,
- InstrItinData<CVI_VM_STU , [InstrStage<1, [SLOT0], 0>,
- InstrStage<1, [SLOT1], 0>,
- InstrStage<1, [CVI_ST], 0>,
- InstrStage<1, [CVI_XLANE]>]>,
- InstrItinData<CVI_HIST , [InstrStage<1, [SLOT0,SLOT1,SLOT2,SLOT3], 0>,
- InstrStage<1, [CVI_ALL]>]>
- ]>;
+ CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
+ CVI_ALL_NOMEM],
+ [Hex_FWD, HVX_FWD], HexagonV60ItinList.ItinList>;
def HexagonModelV60 : SchedMachineModel {
// Max issue per cycle == bundle width.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonScheduleV62.td
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonScheduleV62.td?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonScheduleV62.td (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonScheduleV62.td Wed May 3 15:10:36 2017
@@ -6,115 +6,23 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
+//
+// ScalarItin contains some old itineraries still used by a
+// handful of instructions. Hopefully, we will be able to get rid of them soon.
-// V62 follows the same schedule as V60 with following exceptions:
-// Following instructions are permissible on any slot on V62:
-// V4_J4_cmpeq_fp0_jump_nt
-// V4_J4_cmpeq_fp0_jump_t
-// V4_J4_cmpeq_fp1_jump_nt
-// V4_J4_cmpeq_fp1_jump_t
-// V4_J4_cmpeq_tp0_jump_nt
-// V4_J4_cmpeq_tp0_jump_t
-// V4_J4_cmpeq_tp1_jump_nt
-// V4_J4_cmpeq_tp1_jump_t
-// V4_J4_cmpeqi_fp0_jump_nt
-// V4_J4_cmpeqi_fp0_jump_t
-// V4_J4_cmpeqi_fp1_jump_nt
-// V4_J4_cmpeqi_fp1_jump_t
-// V4_J4_cmpeqi_tp0_jump_nt
-// V4_J4_cmpeqi_tp0_jump_t
-// V4_J4_cmpeqi_tp1_jump_nt
-// V4_J4_cmpeqi_tp1_jump_t
-// V4_J4_cmpeqn1_fp0_jump_nt
-// V4_J4_cmpeqn1_fp0_jump_t
-// V4_J4_cmpeqn1_fp1_jump_nt
-// V4_J4_cmpeqn1_fp1_jump_t
-// V4_J4_cmpeqn1_tp0_jump_nt
-// V4_J4_cmpeqn1_tp0_jump_t
-// V4_J4_cmpeqn1_tp1_jump_nt
-// V4_J4_cmpeqn1_tp1_jump_t
-// V4_J4_cmpgt_fp0_jump_nt
-// V4_J4_cmpgt_fp0_jump_t
-// V4_J4_cmpgt_fp1_jump_nt
-// V4_J4_cmpgt_fp1_jump_t
-// V4_J4_cmpgt_tp0_jump_nt
-// V4_J4_cmpgt_tp0_jump_t
-// V4_J4_cmpgt_tp1_jump_nt
-// V4_J4_cmpgt_tp1_jump_t
-// V4_J4_cmpgti_fp0_jump_nt
-// V4_J4_cmpgti_fp0_jump_t
-// V4_J4_cmpgti_fp1_jump_nt
-// V4_J4_cmpgti_fp1_jump_t
-// V4_J4_cmpgti_tp0_jump_nt
-// V4_J4_cmpgti_tp0_jump_t
-// V4_J4_cmpgti_tp1_jump_nt
-// V4_J4_cmpgti_tp1_jump_t
-// V4_J4_cmpgtn1_fp0_jump_nt
-// V4_J4_cmpgtn1_fp0_jump_t
-// V4_J4_cmpgtn1_fp1_jump_nt
-// V4_J4_cmpgtn1_fp1_jump_t
-// V4_J4_cmpgtn1_tp0_jump_nt
-// V4_J4_cmpgtn1_tp0_jump_t
-// V4_J4_cmpgtn1_tp1_jump_nt
-// V4_J4_cmpgtn1_tp1_jump_t
-// V4_J4_cmpgtu_fp0_jump_nt
-// V4_J4_cmpgtu_fp0_jump_t
-// V4_J4_cmpgtu_fp1_jump_nt
-// V4_J4_cmpgtu_fp1_jump_t
-// V4_J4_cmpgtu_tp0_jump_nt
-// V4_J4_cmpgtu_tp0_jump_t
-// V4_J4_cmpgtu_tp1_jump_nt
-// V4_J4_cmpgtu_tp1_jump_t
-// V4_J4_cmpgtui_fp0_jump_nt
-// V4_J4_cmpgtui_fp0_jump_t
-// V4_J4_cmpgtui_fp1_jump_nt
-// V4_J4_cmpgtui_fp1_jump_t
-// V4_J4_cmpgtui_tp0_jump_nt
-// V4_J4_cmpgtui_tp0_jump_t
-// V4_J4_cmpgtui_tp1_jump_nt
-// V4_J4_cmpgtui_tp1_jump_t
-// V4_J4_tstbit0_fp0_jump_nt
-// V4_J4_tstbit0_fp0_jump_t
-// V4_J4_tstbit0_fp1_jump_nt
-// V4_J4_tstbit0_fp1_jump_t
-// V4_J4_tstbit0_tp0_jump_nt
-// V4_J4_tstbit0_tp0_jump_t
-// V4_J4_tstbit0_tp1_jump_nt
-// V4_J4_tstbit0_tp1_jump_t
-// JMP
-// JMPEXT
-// JMPEXT_f
-// JMPEXT_fnew_nt
-// JMPEXT_fnew_t
-// JMPEXT_t
-// JMPEXT_tnew_nt
-// JMPEXT_tnew_t
-// JMPNOTEXT
-// JMPNOTEXT_f
-// JMPNOTEXT_fnew_nt
-// JMPNOTEXT_fnew_t
-// JMPNOTEXT_t
-// JMPNOTEXT_tnew_nt
-// JMPNOTEXT_tnew_t
-// JMP_f
-// JMP_fnew_nt
-// JMP_fnew_t
-// JMP_t
-// JMP_tnew_nt
-// JMP_tnew_t
-// RESTORE_DEALLOC_RET_JMP_V4
-// RESTORE_DEALLOC_RET_JMP_V4_EXT
-
-def HexagonV62ItinList : ScalarItin, HVXV62Itin {
+def HexagonV62ItinList : DepScalarItinV62, ScalarItin,
+ DepHVXItinV62, HVXItin, PseudoItin {
list<InstrItinData> ItinList =
- !listconcat(ScalarItin_list, HVXV62Itin_list);
+ !listconcat(DepScalarItinV62_list, ScalarItin_list,
+ DepHVXItinV62_list, HVXItin_list, PseudoItin_list);
}
def HexagonItinerariesV62 :
ProcessorItineraries<[SLOT0, SLOT1, SLOT2, SLOT3, SLOT_ENDLOOP,
CVI_ST, CVI_XLANE, CVI_SHIFT, CVI_MPY0, CVI_MPY1,
- CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL],
- [], HexagonV62ItinList.ItinList>;
+ CVI_LD, CVI_XLSHF, CVI_MPY01, CVI_ALL,
+ CVI_ALL_NOMEM],
+ [Hex_FWD, HVX_FWD], HexagonV62ItinList.ItinList>;
def HexagonModelV62 : SchedMachineModel {
// Max issue per cycle == bundle width.
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.cpp Wed May 3 15:10:36 2017
@@ -139,6 +139,59 @@ HexagonSubtarget::HexagonSubtarget(const
UseBSBScheduling = hasV60TOps() && EnableBSBSched;
}
+/// \brief Perform target specific adjustments to the latency of a schedule
+/// dependency.
+void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
+ SDep &Dep) const {
+ MachineInstr *SrcInst = Src->getInstr();
+ MachineInstr *DstInst = Dst->getInstr();
+ if (!Src->isInstr() || !Dst->isInstr())
+ return;
+
+ const HexagonInstrInfo *QII = getInstrInfo();
+
+ // Instructions with .new operands have zero latency.
+ SmallSet<SUnit *, 4> ExclSrc;
+ SmallSet<SUnit *, 4> ExclDst;
+ if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
+ isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
+ Dep.setLatency(0);
+ return;
+ }
+
+ if (!hasV60TOps())
+ return;
+
+ // If it's a REG_SEQUENCE, use its destination instruction to determine
+ // the correct latency.
+ if (DstInst->isRegSequence() && Dst->NumSuccs == 1) {
+ unsigned RSeqReg = DstInst->getOperand(0).getReg();
+ MachineInstr *RSeqDst = Dst->Succs[0].getSUnit()->getInstr();
+ unsigned UseIdx = -1;
+ for (unsigned OpNum = 0; OpNum < RSeqDst->getNumOperands(); OpNum++) {
+ const MachineOperand &MO = RSeqDst->getOperand(OpNum);
+ if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == RSeqReg) {
+ UseIdx = OpNum;
+ break;
+ }
+ }
+ unsigned RSeqLatency = (InstrInfo.getOperandLatency(&InstrItins, *SrcInst,
+ 0, *RSeqDst, UseIdx));
+ Dep.setLatency(RSeqLatency);
+ }
+
+ // Try to schedule uses near definitions to generate .cur.
+ ExclSrc.clear();
+ ExclDst.clear();
+ if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
+ isBestZeroLatency(Src, Dst, QII, ExclSrc, ExclDst)) {
+ Dep.setLatency(0);
+ return;
+ }
+
+ updateLatency(*SrcInst, *DstInst, Dep);
+}
+
void HexagonSubtarget::HexagonDAGMutation::apply(ScheduleDAGInstrs *DAG) {
for (auto &SU : DAG->SUnits) {
@@ -154,19 +207,19 @@ void HexagonSubtarget::HexagonDAGMutatio
for (auto &SU : DAG->SUnits) {
// Update the latency of chain edges between v60 vector load or store
- // instructions to be 1. These instructions cannot be scheduled in the
+ // instructions to be 1. These instruction cannot be scheduled in the
// same packet.
MachineInstr &MI1 = *SU.getInstr();
auto *QII = static_cast<const HexagonInstrInfo*>(DAG->TII);
bool IsStoreMI1 = MI1.mayStore();
bool IsLoadMI1 = MI1.mayLoad();
- if (!QII->isV60VectorInstruction(MI1) || !(IsStoreMI1 || IsLoadMI1))
+ if (!QII->isHVXVec(MI1) || !(IsStoreMI1 || IsLoadMI1))
continue;
for (auto &SI : SU.Succs) {
if (SI.getKind() != SDep::Order || SI.getLatency() != 0)
continue;
MachineInstr &MI2 = *SI.getSUnit()->getInstr();
- if (!QII->isV60VectorInstruction(MI2))
+ if (!QII->isHVXVec(MI2))
continue;
if ((IsStoreMI1 && MI2.mayStore()) || (IsLoadMI1 && MI2.mayLoad())) {
SI.setLatency(1);
@@ -204,69 +257,95 @@ bool HexagonSubtarget::enableMachineSche
return true;
}
-bool HexagonSubtarget::enableSubRegLiveness() const {
- return EnableSubregLiveness;
-}
-
-// This helper function is responsible for increasing the latency only.
void HexagonSubtarget::updateLatency(MachineInstr &SrcInst,
MachineInstr &DstInst, SDep &Dep) const {
+ if (Dep.isArtificial()) {
+ Dep.setLatency(1);
+ return;
+ }
+
if (!hasV60TOps())
return;
auto &QII = static_cast<const HexagonInstrInfo&>(*getInstrInfo());
- if (EnableVecFrwdSched && QII.addLatencyToSchedule(SrcInst, DstInst)) {
- // Vec frwd scheduling.
- Dep.setLatency(Dep.getLatency() + 1);
- } else if (useBSBScheduling() &&
- QII.isLateInstrFeedsEarlyInstr(SrcInst, DstInst)) {
- // BSB scheduling.
- Dep.setLatency(Dep.getLatency() + 1);
- } else if (EnableTCLatencySched) {
- // TClass latency scheduling.
- // Check if SrcInst produces in 2C an operand of DstInst taken in stage 2B.
- if (QII.isTC1(SrcInst) || QII.isTC2(SrcInst))
- if (!QII.isTC1(DstInst) && !QII.isTC2(DstInst))
- Dep.setLatency(Dep.getLatency() + 1);
- }
+ // BSB scheduling.
+ if (QII.isHVXVec(SrcInst) || useBSBScheduling())
+ Dep.setLatency((Dep.getLatency() + 1) >> 1);
}
-/// If the SUnit has a zero latency edge, return the other SUnit.
-static SUnit *getZeroLatency(SUnit *N, SmallVector<SDep, 4> &Deps) {
- for (auto &I : Deps)
- if (I.isAssignedRegDep() && I.getLatency() == 0 &&
- !I.getSUnit()->getInstr()->isPseudo())
- return I.getSUnit();
- return nullptr;
+void HexagonSubtarget::restoreLatency(SUnit *Src, SUnit *Dst) const {
+ MachineInstr *SrcI = Src->getInstr();
+ for (auto &I : Src->Succs) {
+ if (!I.isAssignedRegDep() || I.getSUnit() != Dst)
+ continue;
+ unsigned DepR = I.getReg();
+ int DefIdx = -1;
+ for (unsigned OpNum = 0; OpNum < SrcI->getNumOperands(); OpNum++) {
+ const MachineOperand &MO = SrcI->getOperand(OpNum);
+ if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
+ DefIdx = OpNum;
+ }
+ assert(DefIdx >= 0 && "Def Reg not found in Src MI");
+ MachineInstr *DstI = Dst->getInstr();
+ for (unsigned OpNum = 0; OpNum < DstI->getNumOperands(); OpNum++) {
+ const MachineOperand &MO = DstI->getOperand(OpNum);
+ if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
+ int Latency = (InstrInfo.getOperandLatency(&InstrItins, *SrcI,
+ DefIdx, *DstI, OpNum));
+
+ // For some instructions (ex: COPY), we might end up with < 0 latency
+ // as they don't have any Itinerary class associated with them.
+ if (Latency <= 0)
+ Latency = 1;
+
+ I.setLatency(Latency);
+ updateLatency(*SrcI, *DstI, I);
+ }
+ }
+
+ // Update the latency of opposite edge too.
+ for (auto &J : Dst->Preds) {
+ if (J.getSUnit() != Src)
+ continue;
+ J.setLatency(I.getLatency());
+ }
+ }
}
/// Change the latency between the two SUnits.
-void HexagonSubtarget::changeLatency(SUnit *Src, SmallVector<SDep, 4> &Deps,
- SUnit *Dst, unsigned Lat) const {
- MachineInstr &SrcI = *Src->getInstr();
- for (auto &I : Deps) {
+void HexagonSubtarget::changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat)
+ const {
+ for (auto &I : Src->Succs) {
if (I.getSUnit() != Dst)
continue;
+ SDep T = I;
I.setLatency(Lat);
- SUnit *UpdateDst = I.getSUnit();
- updateLatency(SrcI, *UpdateDst->getInstr(), I);
+
// Update the latency of opposite edge too.
- for (auto &PI : UpdateDst->Preds) {
- if (PI.getSUnit() != Src || !PI.isAssignedRegDep())
- continue;
- PI.setLatency(Lat);
- updateLatency(SrcI, *UpdateDst->getInstr(), PI);
- }
+ T.setSUnit(Src);
+ auto F = std::find(Dst->Preds.begin(), Dst->Preds.end(), T);
+ assert(F != Dst->Preds.end());
+ F->setLatency(I.getLatency());
}
}
+/// If the SUnit has a zero latency edge, return the other SUnit.
+static SUnit *getZeroLatency(SUnit *N, SmallVector<SDep, 4> &Deps) {
+ for (auto &I : Deps)
+ if (I.isAssignedRegDep() && I.getLatency() == 0 &&
+ !I.getSUnit()->getInstr()->isPseudo())
+ return I.getSUnit();
+ return nullptr;
+}
+
// Return true if these are the best two instructions to schedule
// together with a zero latency. Only one dependence should have a zero
// latency. If there are multiple choices, choose the best, and change
-// ther others, if needed.
+// the others, if needed.
bool HexagonSubtarget::isBestZeroLatency(SUnit *Src, SUnit *Dst,
- const HexagonInstrInfo *TII) const {
+ const HexagonInstrInfo *TII, SmallSet<SUnit*, 4> &ExclSrc,
+ SmallSet<SUnit*, 4> &ExclDst) const {
MachineInstr &SrcInst = *Src->getInstr();
MachineInstr &DstInst = *Dst->getInstr();
@@ -277,6 +356,16 @@ bool HexagonSubtarget::isBestZeroLatency
if (SrcInst.isPHI() || DstInst.isPHI())
return false;
+ if (!TII->isToBeScheduledASAP(SrcInst, DstInst) &&
+ !TII->canExecuteInBundle(SrcInst, DstInst))
+ return false;
+
+ // The architecture doesn't allow three dependent instructions in the same
+ // packet. So, if the destination has a zero latency successor, then it's
+ // not a candidate for a zero latency predecessor.
+ if (getZeroLatency(Dst, Dst->Succs) != nullptr)
+ return false;
+
// Check if the Dst instruction is the best candidate first.
SUnit *Best = nullptr;
SUnit *DstBest = nullptr;
@@ -290,98 +379,53 @@ bool HexagonSubtarget::isBestZeroLatency
if (Best != Dst)
return false;
- // The caller frequents adds the same dependence twice. If so, then
+ // The caller frequently adds the same dependence twice. If so, then
// return true for this case too.
- if (Src == SrcBest && Dst == DstBest)
+ if ((Src == SrcBest && Dst == DstBest ) ||
+ (SrcBest == nullptr && Dst == DstBest) ||
+ (Src == SrcBest && Dst == nullptr))
return true;
// Reassign the latency for the previous bests, which requires setting
// the dependence edge in both directions.
- if (SrcBest != nullptr)
- changeLatency(SrcBest, SrcBest->Succs, Dst, 1);
- if (DstBest != nullptr)
- changeLatency(Src, Src->Succs, DstBest, 1);
- // If there is an edge from SrcBest to DstBst, then try to change that
- // to 0 now.
- if (SrcBest && DstBest)
- changeLatency(SrcBest, SrcBest->Succs, DstBest, 0);
-
- return true;
-}
-
-// Update the latency of a Phi when the Phi bridges two instructions that
-// require a multi-cycle latency.
-void HexagonSubtarget::changePhiLatency(MachineInstr &SrcInst, SUnit *Dst,
- SDep &Dep) const {
- if (!SrcInst.isPHI() || Dst->NumPreds == 0 || Dep.getLatency() != 0)
- return;
-
- for (const SDep &PI : Dst->Preds) {
- if (PI.getLatency() != 0)
- continue;
- Dep.setLatency(2);
- break;
+ if (SrcBest != nullptr) {
+ if (!hasV60TOps())
+ changeLatency(SrcBest, Dst, 1);
+ else
+ restoreLatency(SrcBest, Dst);
}
-}
-
-/// \brief Perform target specific adjustments to the latency of a schedule
-/// dependency.
-void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst,
- SDep &Dep) const {
- MachineInstr *SrcInst = Src->getInstr();
- MachineInstr *DstInst = Dst->getInstr();
- if (!Src->isInstr() || !Dst->isInstr())
- return;
-
- const HexagonInstrInfo *QII = static_cast<const HexagonInstrInfo *>(getInstrInfo());
-
- // Instructions with .new operands have zero latency.
- if (QII->canExecuteInBundle(*SrcInst, *DstInst) &&
- isBestZeroLatency(Src, Dst, QII)) {
- Dep.setLatency(0);
- return;
- }
-
- if (!hasV60TOps())
- return;
-
- // Don't adjust the latency of post-increment part of the instruction.
- if (QII->isPostIncrement(*SrcInst) && Dep.isAssignedRegDep()) {
- if (SrcInst->mayStore())
- return;
- if (Dep.getReg() != SrcInst->getOperand(0).getReg())
- return;
- } else if (QII->isPostIncrement(*DstInst) && Dep.getKind() == SDep::Anti) {
- if (DstInst->mayStore())
- return;
- if (Dep.getReg() != DstInst->getOperand(0).getReg())
- return;
- } else if (QII->isPostIncrement(*DstInst) && DstInst->mayStore() &&
- Dep.isAssignedRegDep()) {
- MachineOperand &Op = DstInst->getOperand(DstInst->getNumOperands() - 1);
- if (Op.isReg() && Dep.getReg() != Op.getReg())
- return;
- }
-
- // Check if we need to change any the latency values when Phis are added.
- if (useBSBScheduling() && SrcInst->isPHI()) {
- changePhiLatency(*SrcInst, Dst, Dep);
- return;
+ if (DstBest != nullptr) {
+ if (!hasV60TOps())
+ changeLatency(Src, DstBest, 1);
+ else
+ restoreLatency(Src, DstBest);
}
- // If it's a REG_SEQUENCE, use its destination instruction to determine
- // the correct latency.
- if (DstInst->isRegSequence() && Dst->NumSuccs == 1)
- DstInst = Dst->Succs[0].getSUnit()->getInstr();
-
- // Try to schedule uses near definitions to generate .cur.
- if (EnableDotCurSched && QII->isToBeScheduledASAP(*SrcInst, *DstInst) &&
- isBestZeroLatency(Src, Dst, QII)) {
- Dep.setLatency(0);
- return;
+ // Attempt to find another opprotunity for zero latency in a different
+ // dependence.
+ if (SrcBest && DstBest)
+ // If there is an edge from SrcBest to DstBst, then try to change that
+ // to 0 now.
+ changeLatency(SrcBest, DstBest, 0);
+ else if (DstBest) {
+ // Check if the previous best destination instruction has a new zero
+ // latency dependence opportunity.
+ ExclSrc.insert(Src);
+ for (auto &I : DstBest->Preds)
+ if (ExclSrc.count(I.getSUnit()) == 0 &&
+ isBestZeroLatency(I.getSUnit(), DstBest, TII, ExclSrc, ExclDst))
+ changeLatency(I.getSUnit(), DstBest, 0);
+ } else if (SrcBest) {
+ // Check if previous best source instruction has a new zero latency
+ // dependence opportunity.
+ ExclDst.insert(Dst);
+ for (auto &I : SrcBest->Succs)
+ if (ExclDst.count(I.getSUnit()) == 0 &&
+ isBestZeroLatency(SrcBest, I.getSUnit(), TII, ExclSrc, ExclDst))
+ changeLatency(SrcBest, I.getSUnit(), 0);
}
- updateLatency(*SrcInst, *DstInst, Dep);
+ return true;
}
unsigned HexagonSubtarget::getL1CacheLineSize() const {
@@ -392,3 +436,7 @@ unsigned HexagonSubtarget::getL1Prefetch
return 32;
}
+bool HexagonSubtarget::enableSubRegLiveness() const {
+ return EnableSubregLiveness;
+}
+
Modified: llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonSubtarget.h Wed May 3 15:10:36 2017
@@ -146,11 +146,10 @@ private:
// Helper function responsible for increasing the latency only.
void updateLatency(MachineInstr &SrcInst, MachineInstr &DstInst, SDep &Dep)
const;
- void changeLatency(SUnit *Src, SmallVector<SDep, 4> &Deps, SUnit *Dst,
- unsigned Lat) const;
- bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII)
- const;
- void changePhiLatency(MachineInstr &SrcInst, SUnit *Dst, SDep &Dep) const;
+ void restoreLatency(SUnit *Src, SUnit *Dst) const;
+ void changeLatency(SUnit *Src, SUnit *Dst, unsigned Lat) const;
+ bool isBestZeroLatency(SUnit *Src, SUnit *Dst, const HexagonInstrInfo *TII,
+ SmallSet<SUnit*, 4> &ExclSrc, SmallSet<SUnit*, 4> &ExclDst) const;
};
} // end namespace llvm
Modified: llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/HexagonVLIWPacketizer.cpp Wed May 3 15:10:36 2017
@@ -334,7 +334,7 @@ bool HexagonPacketizerList::isNewifiable
// Vector stores can be predicated, and can be new-value stores, but
// they cannot be predicated on a .new predicate value.
if (NewRC == &Hexagon::PredRegsRegClass)
- if (HII->isV60VectorInstruction(MI) && MI.mayStore())
+ if (HII->isHVXVec(MI) && MI.mayStore())
return false;
return HII->isCondInst(MI) || HII->isJumpR(MI) || MI.isReturn() ||
HII->mayBeNewStore(MI);
@@ -377,9 +377,9 @@ void HexagonPacketizerList::cleanUpDotCu
bool HexagonPacketizerList::canPromoteToDotCur(const MachineInstr &MI,
const SUnit *PacketSU, unsigned DepReg, MachineBasicBlock::iterator &MII,
const TargetRegisterClass *RC) {
- if (!HII->isV60VectorInstruction(MI))
+ if (!HII->isHVXVec(MI))
return false;
- if (!HII->isV60VectorInstruction(*MII))
+ if (!HII->isHVXVec(*MII))
return false;
// Already a dot new instruction.
@@ -1365,7 +1365,7 @@ bool HexagonPacketizerList::isLegalToPac
// Data dpendence ok if we have load.cur.
if (DepType == SDep::Data && HII->isDotCurInst(J)) {
- if (HII->isV60VectorInstruction(I))
+ if (HII->isHVXVec(I))
continue;
}
@@ -1374,6 +1374,8 @@ bool HexagonPacketizerList::isLegalToPac
if (canPromoteToDotNew(I, SUJ, DepReg, II, RC)) {
if (promoteToDotNew(I, DepType, II, RC)) {
PromotedToDotNew = true;
+ if (cannotCoexist(I, J))
+ FoundSequentialDependence = true;
continue;
}
}
@@ -1418,26 +1420,7 @@ bool HexagonPacketizerList::isLegalToPac
DepType != SDep::Output)
continue;
- // Ignore output dependences due to superregs. We can write to two
- // different subregisters of R1:0 for instance in the same cycle.
-
- // If neither I nor J defines DepReg, then this is a superfluous output
- // dependence. The dependence must be of the form:
- // R0 = ...
- // R1 = ...
- // and there is an output dependence between the two instructions with
- // DepReg = D0.
- // We want to ignore these dependences. Ideally, the dependence
- // constructor should annotate such dependences. We can then avoid this
- // relatively expensive check.
- //
if (DepType == SDep::Output) {
- // DepReg is the register that's responsible for the dependence.
- unsigned DepReg = SUJ->Succs[i].getReg();
-
- // Check if I and J really defines DepReg.
- if (!I.definesRegister(DepReg) && !J.definesRegister(DepReg))
- continue;
FoundSequentialDependence = true;
break;
}
@@ -1553,10 +1536,9 @@ bool HexagonPacketizerList::isLegalToPru
MachineInstr &I = *SUI->getInstr();
MachineInstr &J = *SUJ->getInstr();
- if (cannotCoexist(I, J))
- return false;
+ bool Coexist = !cannotCoexist(I, J);
- if (!Dependence)
+ if (Coexist && !Dependence)
return true;
// Check if the instruction was promoted to a dot-new. If so, demote it
@@ -1659,21 +1641,6 @@ bool HexagonPacketizerList::shouldAddToP
}
-// Return true when ConsMI uses a register defined by ProdMI.
-static bool isDependent(const MachineInstr &ProdMI,
- const MachineInstr &ConsMI) {
- if (!ProdMI.getOperand(0).isReg())
- return false;
- unsigned DstReg = ProdMI.getOperand(0).getReg();
-
- for (auto &Op : ConsMI.operands())
- if (Op.isReg() && Op.isUse() && Op.getReg() == DstReg)
- // The MIs depend on each other.
- return true;
-
- return false;
-}
-
// V60 forward scheduling.
bool HexagonPacketizerList::producesStall(const MachineInstr &I) {
// If the packet already stalls, then ignore the stall from a subsequent
@@ -1695,40 +1662,48 @@ bool HexagonPacketizerList::producesStal
return false;
}
- // Check for stall between two vector instructions.
- if (HII->isV60VectorInstruction(I)) {
- for (auto J : OldPacketMIs) {
- if (!HII->isV60VectorInstruction(*J))
- continue;
- if (isDependent(*J, I) && !HII->isVecUsableNextPacket(*J, I))
- return true;
- }
+ SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
- return false;
- }
+ // Check if the latency is 0 between this instruction and any instruction
+ // in the current packet. If so, we disregard any potential stalls due to
+ // the instructions in the previous packet. Most of the instruction pairs
+ // that can go together in the same packet have 0 latency between them.
+ // Only exceptions are newValueJumps as they're generated much later and
+ // the latencies can't be changed at that point. Another is .cur
+ // instructions if its consumer has a 0 latency successor (such as .new).
+ // In this case, the latency between .cur and the consumer stays non-zero
+ // even though we can have both .cur and .new in the same packet. Changing
+ // the latency to 0 is not an option as it causes software pipeliner to
+ // not pipeline in some cases.
- // Check for stall between two scalar instructions. First, check that
- // there is no definition of a use in the current packet, because it
- // may be a candidate for .new.
- for (auto J : CurrentPacketMIs)
- if (!HII->isV60VectorInstruction(*J) && isDependent(*J, I))
- return false;
+ // For Example:
+ // {
+ // I1: v6.cur = vmem(r0++#1)
+ // I2: v7 = valign(v6,v4,r2)
+ // I3: vmem(r5++#1) = v7.new
+ // }
+ // Here I2 and I3 has 0 cycle latency, but I1 and I2 has 2.
- // Check for stall between I and instructions in the previous packet.
- if (MF.getSubtarget<HexagonSubtarget>().useBSBScheduling()) {
- for (auto J : OldPacketMIs) {
- if (HII->isV60VectorInstruction(*J))
- continue;
- if (!HII->isLateInstrFeedsEarlyInstr(*J, I))
- continue;
- if (isDependent(*J, I) && !HII->canExecuteInBundle(*J, I))
+ for (auto J : CurrentPacketMIs) {
+ SUnit *SUJ = MIToSUnit[J];
+ for (auto &Pred : SUI->Preds)
+ if (Pred.getSUnit() == SUJ &&
+ (Pred.getLatency() == 0 || HII->isNewValueJump(I) ||
+ HII->isToBeScheduledASAP(*J, I)))
+ return false;
+ }
+
+ // Check if the latency is greater than one between this instruction and any
+ // instruction in the previous packet.
+ for (auto J : OldPacketMIs) {
+ SUnit *SUJ = MIToSUnit[J];
+ for (auto &Pred : SUI->Preds)
+ if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1)
return true;
- }
}
// Check if the latency is greater than one between this instruction and any
// instruction in the previous packet.
- SUnit *SUI = MIToSUnit[const_cast<MachineInstr *>(&I)];
for (auto J : OldPacketMIs) {
SUnit *SUJ = MIToSUnit[J];
for (auto &Pred : SUI->Preds)
@@ -1739,7 +1714,6 @@ bool HexagonPacketizerList::producesStal
return false;
}
-
//===----------------------------------------------------------------------===//
// Public Constructor Functions
//===----------------------------------------------------------------------===//
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h Wed May 3 15:10:36 2017
@@ -29,7 +29,7 @@ namespace llvm {
///
namespace HexagonII {
unsigned const TypeCVI_FIRST = TypeCVI_HIST;
- unsigned const TypeCVI_LAST = TypeCVI_VX_DV;
+ unsigned const TypeCVI_LAST = TypeCVI_VX_LATE;
enum SubTarget {
HasV4SubT = 0x3f,
Modified: llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp (original)
+++ llvm/trunk/lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp Wed May 3 15:10:36 2017
@@ -102,12 +102,13 @@ void HexagonCVIResource::SetupTUL(TypeUn
UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
(*TUL)[HexagonII::TypeCVI_VA_DV] = UnitsAndLanes(CVI_XLANE | CVI_MPY0, 2);
(*TUL)[HexagonII::TypeCVI_VX] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1);
+ (*TUL)[HexagonII::TypeCVI_VX_LATE] = UnitsAndLanes(CVI_MPY0 | CVI_MPY1, 1);
(*TUL)[HexagonII::TypeCVI_VX_DV] = UnitsAndLanes(CVI_MPY0, 2);
(*TUL)[HexagonII::TypeCVI_VP] = UnitsAndLanes(CVI_XLANE, 1);
(*TUL)[HexagonII::TypeCVI_VP_VS] = UnitsAndLanes(CVI_XLANE, 2);
(*TUL)[HexagonII::TypeCVI_VS] = UnitsAndLanes(CVI_SHIFT, 1);
(*TUL)[HexagonII::TypeCVI_VINLANESAT] =
- (CPU == "hexagonv60" || CPU == "hexagonv61" || CPU == "hexagonv61v1")
+ (CPU == "hexagonv60")
? UnitsAndLanes(CVI_SHIFT, 1)
: UnitsAndLanes(CVI_XLANE | CVI_SHIFT | CVI_MPY0 | CVI_MPY1, 1);
(*TUL)[HexagonII::TypeCVI_VM_LD] =
@@ -291,10 +292,8 @@ bool HexagonShuffler::check() {
break;
case HexagonII::TypeNCJ:
++memory; // NV insns are memory-like.
- if (HexagonMCInstrInfo::getDesc(MCII, ID).isBranch()) {
- ++jumps, ++jump1;
- foundBranches.push_back(ISJ);
- }
+ ++jumps, ++jump1;
+ foundBranches.push_back(ISJ);
break;
case HexagonII::TypeV2LDST:
if (HexagonMCInstrInfo::getDesc(MCII, ID).mayLoad()) {
Modified: llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll?rev=302073&r1=302072&r2=302073&view=diff
==============================================================================
--- llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll (original)
+++ llvm/trunk/test/CodeGen/Hexagon/swp-matmul-bitext.ll Wed May 3 15:10:36 2017
@@ -1,17 +1,16 @@
-; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-bsb-sched=0 -enable-pipeliner < %s | FileCheck %s
-; RUN: llc -march=hexagon -mcpu=hexagonv5 -enable-pipeliner < %s | FileCheck %s
+; RUN: llc -march=hexagon -mcpu=hexagonv60 -enable-pipeliner < %s | FileCheck %s
; From coremark. Test that we pipeline the matrix multiplication bitextract
; function. The pipelined code should have two packets.
; CHECK: loop0(.LBB0_[[LOOP:.]],
; CHECK: .LBB0_[[LOOP]]:
-; CHECK: = extractu([[REG2:(r[0-9]+)]],
-; CHECK: = extractu([[REG2]],
-; CHECK: [[REG0:(r[0-9]+)]] = memh
-; CHECK: [[REG1:(r[0-9]+)]] = memh
+; CHECK: [[REG0:(r[0-9]+)]] = mpyi([[REG1:(r[0-9]+)]],[[REG2:(r[0-9]+)]])
; CHECK: += mpyi
-; CHECK: [[REG2]] = mpyi([[REG0]],[[REG1]])
+; CHECK: [[REG1:(r[0-9]+)]] = memh
+; CHECK: = extractu([[REG0:(r[0-9]+)]],
+; CHECK: = extractu([[REG0]],
+; CHECK: [[REG2:(r[0-9]+)]] = memh
; CHECK: endloop0
%union_h2_sem_t = type { i32 }
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