[llvm] r302049 - [X86][LWP] Add stack folding mappings and tests for LWPINS/LWPVAL instructions

[Simon Pilgrim via llvm-commits]

Author: rksimon
Date: Wed May  3 11:46:30 2017
New Revision: 302049

URL: http://llvm.org/viewvc/llvm-project?rev=302049&view=rev
Log:
[X86][LWP] Add stack folding mappings and tests for LWPINS/LWPVAL instructions

Added:
    llvm/trunk/test/CodeGen/X86/stack-folding-lwp.ll
Modified:
    llvm/trunk/lib/Target/X86/X86InstrInfo.cpp

Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=302049&r1=302048&r2=302049&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Wed May  3 11:46:30 2017
@@ -821,6 +821,12 @@ X86InstrInfo::X86InstrInfo(X86Subtarget
     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
 
+    // LWP foldable instructions
+    { X86::LWPINS32rri,        X86::LWPINS32rmi,      0 },
+    { X86::LWPINS64rri,        X86::LWPINS64rmi,      0 },
+    { X86::LWPVAL32rri,        X86::LWPVAL32rmi,      0 },
+    { X86::LWPVAL64rri,        X86::LWPVAL64rmi,      0 },
+
     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },

Added: llvm/trunk/test/CodeGen/X86/stack-folding-lwp.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/X86/stack-folding-lwp.ll?rev=302049&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/X86/stack-folding-lwp.ll (added)
+++ llvm/trunk/test/CodeGen/X86/stack-folding-lwp.ll Wed May  3 11:46:30 2017
@@ -0,0 +1,49 @@
+; RUN: llc -O3 -disable-peephole -mtriple=x86_64-unknown-unknown -mattr=+lwp < %s | FileCheck %s
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-unknown"
+
+; Stack reload folding tests.
+;
+; By including a nop call with sideeffects we can force a partial register spill of the
+; relevant registers and check that the reload is correctly folded into the instruction.
+
+define i8 @stack_fold_lwpins_u32(i32 %a0, i32 %a1) {
+; CHECK-LABEL: stack_fold_lwpins_u32
+; CHECK:       # BB#0:
+; CHECK:       lwpins $2814, {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = tail call i8 @llvm.x86.lwpins32(i32 %a0, i32 %a1, i32 2814)
+  ret i8 %2
+}
+declare i8 @llvm.x86.lwpins32(i32, i32, i32)
+
+define i8 @stack_fold_lwpins_u64(i64 %a0, i32 %a1) {
+; CHECK-LABEL: stack_fold_lwpins_u64
+; CHECK:       # BB#0:
+; CHECK:       lwpins $2814, {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  %2 = tail call i8 @llvm.x86.lwpins64(i64 %a0, i32 %a1, i32 2814)
+  ret i8 %2
+}
+declare i8 @llvm.x86.lwpins64(i64, i32, i32)
+
+define void @stack_fold_lwpval_u32(i32 %a0, i32 %a1) {
+; CHECK-LABEL: stack_fold_lwpval_u32
+; CHECK:       # BB#0:
+; CHECK:       lwpval $2814, {{-?[0-9]*}}(%rsp), %eax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  tail call void @llvm.x86.lwpval32(i32 %a0, i32 %a1, i32 2814)
+  ret void
+}
+declare void @llvm.x86.lwpval32(i32, i32, i32)
+
+define void @stack_fold_lwpval_u64(i64 %a0, i32 %a1) {
+; CHECK-LABEL: stack_fold_lwpval_u64
+; CHECK:       # BB#0:
+; CHECK:       lwpval $2814, {{-?[0-9]*}}(%rsp), %rax {{.*#+}} 4-byte Folded Reload
+  %1 = tail call i64 asm sideeffect "nop", "=x,~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+  tail call void @llvm.x86.lwpval64(i64 %a0, i32 %a1, i32 2814)
+  ret void
+}
+declare void @llvm.x86.lwpval64(i64, i32, i32)