[PATCH] D32802: Add checks so that -pre-RA-sched=list-ilp does not crash on SystemZ (Bug 32723).

[Jonas Paulsson via Phabricator via llvm-commits]

jonpa created this revision.
Herald added a subscriber: MatzeB.

Due to the current use in the SystemZ backend of MVT::Untyped, the list-ilp scheduler will crash when it does look ups like

  TLI->getRepRegClassFor(VT)->getID();

This patch adds checks for MVT::Untyped in the places needed to avoid compiler crashes resulting when VT is Untyped.

Discussion on https://bugs.llvm.org//show_bug.cgi?id=32723. (This was posted on llvm-commits last week also without reply)


https://reviews.llvm.org/D32802

Files:
  lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
  test/CodeGen/SystemZ/list-ilp-crash.ll


Index: test/CodeGen/SystemZ/list-ilp-crash.ll
===================================================================
--- /dev/null
+++ test/CodeGen/SystemZ/list-ilp-crash.ll
@@ -0,0 +1,23 @@
+; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 -pre-RA-sched=list-ilp | FileCheck %s
+;
+; Check that list-ilp scheduler does not crash due to SystemZ's current use
+; of MVT::Untyped.
+
+define void @pr32723(i8) {
+; CHECK: .text
+BB:
+  br label %CF245
+
+CF245:                                            ; preds = %CF245, %BB
+  %Shuff57 = shufflevector <4 x i8> zeroinitializer, <4 x i8> zeroinitializer, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
+  %Cmp84 = icmp uge i8 %0, undef
+  br i1 %Cmp84, label %CF245, label %CF260
+
+CF260:                                            ; preds = %CF245
+  %B156 = sdiv <4 x i8> %Shuff57, %Shuff57
+  br label %CF255
+
+CF255:                                            ; preds = %CF255, %CF260
+  %I186 = insertelement <4 x i8> %B156, i8 %0, i32 2
+  br label %CF255
+}
Index: lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1978,7 +1978,7 @@
   unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
   for (unsigned i = 0; i != NumDefs; ++i) {
     MVT VT = N->getSimpleValueType(i);
-    if (!N->hasAnyUseOfValue(i))
+    if (!N->hasAnyUseOfValue(i) || VT == MVT::Untyped)
       continue;
     unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
     if (RegPressure[RCId] >= RegLimit[RCId])
@@ -2011,6 +2011,8 @@
     for (ScheduleDAGSDNodes::RegDefIter RegDefPos(PredSU, scheduleDAG);
          RegDefPos.IsValid(); RegDefPos.Advance()) {
       MVT VT = RegDefPos.GetValue();
+      if (VT == MVT::Untyped)
+        continue;
       unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
       if (RegPressure[RCId] >= RegLimit[RCId])
         ++PDiff;
@@ -2024,7 +2026,7 @@
   unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
   for (unsigned i = 0; i != NumDefs; ++i) {
     MVT VT = N->getSimpleValueType(i);
-    if (!N->hasAnyUseOfValue(i))
+    if (!N->hasAnyUseOfValue(i) || VT == MVT::Untyped)
       continue;
     unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
     if (RegPressure[RCId] >= RegLimit[RCId])
@@ -2133,6 +2135,8 @@
     if (!PN->isMachineOpcode()) {
       if (PN->getOpcode() == ISD::CopyFromReg) {
         MVT VT = PN->getSimpleValueType(0);
+        if (VT == MVT::Untyped)
+          continue;
         unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
         RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
       }
@@ -2145,14 +2149,16 @@
         POpc == TargetOpcode::INSERT_SUBREG ||
         POpc == TargetOpcode::SUBREG_TO_REG) {
       MVT VT = PN->getSimpleValueType(0);
+      if (VT == MVT::Untyped)
+        continue;
       unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
       RegPressure[RCId] += TLI->getRepRegClassCostFor(VT);
       continue;
     }
     unsigned NumDefs = TII->get(PN->getMachineOpcode()).getNumDefs();
     for (unsigned i = 0; i != NumDefs; ++i) {
       MVT VT = PN->getSimpleValueType(i);
-      if (!PN->hasAnyUseOfValue(i))
+      if (!PN->hasAnyUseOfValue(i) || VT == MVT::Untyped)
         continue;
       unsigned RCId = TLI->getRepRegClassFor(VT)->getID();
       if (RegPressure[RCId] < TLI->getRepRegClassCostFor(VT))
@@ -2169,7 +2175,7 @@
     unsigned NumDefs = TII->get(N->getMachineOpcode()).getNumDefs();
     for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
       MVT VT = N->getSimpleValueType(i);
-      if (VT == MVT::Glue || VT == MVT::Other)
+      if (VT == MVT::Glue || VT == MVT::Other || VT == MVT::Untyped)
         continue;
       if (!N->hasAnyUseOfValue(i))
         continue;


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