[PATCH] D32679: [X86][AVX-512] Allow EVEX encoded instruction selection when available for mul v8i32.

[Igor Breger via Phabricator via llvm-commits]

igorb added a comment.

I think we can base the predicate checks on encoding and "EVEX TO VEX Compression". I will  pre-commit changes to avx512vl-arith.ll if the approach is acceptable.
In GlobalIsel https://reviews.llvm.org/D32698 i explicit check every  instruction selection.



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Comment at: test/CodeGen/X86/avx-isa-check.ll:683
 }
+
+define <8 x i32> @test_mul_v8i32(<8 x i32> %arg1, <8 x i32> %arg2) #0 {
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craig.topper wrote:
> What is this test really testing? Just that isel doesn't fail if you do a v8i32 mul with various isel combinations? It doesn't look like it tests which instruction is emitted. Would this test case even fail if you put it in with no other changes? If that's correct I think we should have a test that checks which instruction is emitted.
yes,  It only check  that isel doesn't fail with various isel combinations.


https://reviews.llvm.org/D32679