[PATCH] D32756: [DAGCombine] Refacotr common addcarry pattern.
Amaury SECHET via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue May 2 10:14:40 PDT 2017
deadalnix created this revision.
This pattern is no very useful per se, but it exposes optimization for toehr patterns that wouldn't kick in otherwize. It's very common and worth optimizing for.
https://reviews.llvm.org/D32756
Files:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
test/CodeGen/X86/addcarry.ll
Index: test/CodeGen/X86/addcarry.ll
===================================================================
--- test/CodeGen/X86/addcarry.ll
+++ test/CodeGen/X86/addcarry.ll
@@ -86,21 +86,14 @@
define %scalar @pr31719(%scalar* nocapture readonly %this, %scalar %arg.b) {
; CHECK-LABEL: pr31719:
; CHECK: # BB#0: # %entry
-; CHECK-NEXT: addq 8(%rsi), %rcx
-; CHECK-NEXT: sbbq %r10, %r10
-; CHECK-NEXT: andl $1, %r10d
-; CHECK-NEXT: addq 16(%rsi), %r8
-; CHECK-NEXT: sbbq %rax, %rax
-; CHECK-NEXT: andl $1, %eax
-; CHECK-NEXT: addq 24(%rsi), %r9
; CHECK-NEXT: addq (%rsi), %rdx
-; CHECK-NEXT: adcq $0, %rcx
-; CHECK-NEXT: adcq %r8, %r10
-; CHECK-NEXT: adcq %r9, %rax
+; CHECK-NEXT: adcq 8(%rsi), %rcx
+; CHECK-NEXT: adcq 16(%rsi), %r8
+; CHECK-NEXT: adcq 24(%rsi), %r9
; CHECK-NEXT: movq %rdx, (%rdi)
; CHECK-NEXT: movq %rcx, 8(%rdi)
-; CHECK-NEXT: movq %r10, 16(%rdi)
-; CHECK-NEXT: movq %rax, 24(%rdi)
+; CHECK-NEXT: movq %r8, 16(%rdi)
+; CHECK-NEXT: movq %r9, 24(%rdi)
; CHECK-NEXT: movq %rdi, %rax
; CHECK-NEXT: retq
entry:
Index: lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2163,6 +2163,29 @@
N0.getOperand(0), N0.getOperand(1), CarryIn);
}
+ // This is a convoluted pattern, but it is actually common
+ // when legalizing big int additions.
+ // (addcarry X, (addcarry 0, 0, Y:Carry), (addcarry Y, 0, Z):Carry)
+ // -> (addcarry X, 0, (addcarry A, B, Z):Carry)
+ // With Y = (uaddo A, B)
+ if (N1.getOpcode() == ISD::ADDCARRY &&
+ isNullConstant(N1.getOperand(0)) &&
+ isNullConstant(N1.getOperand(1)) &&
+ CarryIn.getOpcode() == ISD::ADDCARRY &&
+ isNullConstant(CarryIn.getOperand(1))) {
+ auto Y = CarryIn.getOperand(0);
+ if (Y.getOpcode() == ISD::UADDO &&
+ N1.getOperand(2).getNode() == Y.getNode()) {
+ auto NewY = DAG.getNode(ISD::ADDCARRY, SDLoc(N), Y->getVTList(),
+ Y.getOperand(0), Y.getOperand(1),
+ CarryIn.getOperand(2));
+ AddToWorklist(NewY.getNode());
+ return DAG.getNode(ISD::ADDCARRY, SDLoc(N), N->getVTList(), N0,
+ DAG.getConstant(0, SDLoc(N), N0.getValueType()),
+ NewY.getValue(1));
+ }
+ }
+
return SDValue();
}
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D32756.97468.patch
Type: text/x-patch
Size: 2481 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20170502/d23e122f/attachment.bin>
More information about the llvm-commits
mailing list