[PATCH] D32620: [DAGCombiner] shrink/widen a vselect to match its condition operand size (PR14657)

[Nadav Rotem via Phabricator via llvm-commits]

nadav added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6935
+  // not want to create an illegal select.
+  if (SetCCVT.getScalarSizeInBits() != VT.getScalarSizeInBits() ||
+      !TLI.isOperationLegalOrCustom(ISD::VSELECT, VT))
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I think that it can be a good idea to check which DAGCombine phase we are in and make sure that we are in the pre-legalization phase. 


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Comment at: lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6945
+    // FP_ROUND (fptrunc) has an extra operand.
+    SDValue CastOp1 = DAG.getNode(CastOpcode, DL, VT, SelOp1, N->getOperand(1));
+    SDValue CastOp2 = DAG.getNode(CastOpcode, DL, VT, SelOp2, N->getOperand(1));
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I think that we should check that a and b have one use. 


https://reviews.llvm.org/D32620