[PATCH] D32219: [X86][SSE] Improve DIV/SQRT throughput estimates for SB/HW schedule models

Gadi Haber via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 27 05:08:08 PDT 2017


gadi.haber added inline comments.


================
Comment at: lib/Target/X86/X86SchedHaswell.td:140
+def : WriteRes<WriteFDiv, [HWPort0]> {
+  let Latency = 12; // 10-14 cycles.
+  let ResourceCycles = [12];
----------------
instruction latency of X87 FDIV in Haswell is actually higher and takes 20 cycles


================
Comment at: lib/Target/X86/X86SchedHaswell.td:141
+  let Latency = 12; // 10-14 cycles.
+  let ResourceCycles = [12];
+  let NumMicroOps = 1;
----------------
I believe ResourceCycles here should be 1.



================
Comment at: lib/Target/X86/X86SchedHaswell.td:145
+def : WriteRes<WriteFDivLd, [HWPort23, HWPort0]> {
+  let Latency = 16; // load + 10-14 cycles.
+  let ResourceCycles = [1, 12];
----------------
latency of FDIVLd in Haswell is 24


================
Comment at: lib/Target/X86/X86SchedHaswell.td:146
+  let Latency = 16; // load + 10-14 cycles.
+  let ResourceCycles = [1, 12];
+  let NumMicroOps = 2;
----------------
ResourceCycles for FDIVLd is [1, 1]


================
Comment at: lib/Target/X86/X86SchedHaswell.td:151
+def : WriteRes<WriteFSqrt, [HWPort0]> {
+  let Latency = 15;
+  let ResourceCycles = [15];
----------------
latency of FSqrt in Haswell is 23


================
Comment at: lib/Target/X86/X86SchedHaswell.td:156
+def : WriteRes<WriteFSqrtLd, [HWPort23, HWPort0]> {
+  let Latency = 19;
+  let ResourceCycles = [1, 15];
----------------
I don't have the exact latency for Haswell but is larger than 23


================
Comment at: lib/Target/X86/X86SchedHaswell.td:157
+  let Latency = 19;
+  let ResourceCycles = [1, 15];
+  let NumMicroOps = 2;
----------------
ResourceCycles is [1, 1]


================
Comment at: lib/Target/X86/X86SchedHaswell.td:1926
 // y,y,y.
 def WriteVDIVPSYrr : SchedWriteRes<[HWPort0, HWPort15]> {
   let Latency = 19; // 18-21 cycles.
----------------
HWPort15 should actually be changed to HWPort015 in Haswell


================
Comment at: lib/Target/X86/X86SchedHaswell.td:1929
   let NumMicroOps = 3;
-  let ResourceCycles = [2, 1];
+  let ResourceCycles = [2, 19];
 }
----------------
ResourceCycles should be [2, 1]

ResourceCycles lists the number of times where HW port was used in the instruction.
In this case HWPort0 is used twice (by uOp1 and uOp2) and HWPort015 is used only once (by uOp3)


Repository:
  rL LLVM

https://reviews.llvm.org/D32219





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