[PATCH] D28249: Improve scheduling with branch coalescing

[Eric Christopher via Phabricator via llvm-commits]

echristo added a comment.

Hi Matthias,

I'll let Lei talk to more of it, however...

In https://reviews.llvm.org/D28249#723145, @MatzeB wrote:

> Just noticed we have a new pass in the codegen pipeline and wondered what it is about. Some comments:
>
> - The description/examples talk about the same branch condition in the IR but the IR doesn't even have branches and this is an MI pass, not an IR pass.


Would you prefer s/IR/MIR? :)

That said, it's definitely meant to be an MI pass.

> - When I codegen the given example on X86 I do indeed see silly code getting generated because isel chooses a "CMOV_FR64" for each of the select instructions which "Expand ISel Pseudo-instructions" later expands into 3 if-diamonds that all have the same condition.

Yep. The arm and mips backends also do the same thing.

> - It looks like we created a whole new pass to fix Expand ISel Pseudo begin stupid?

I agree up to a point, though I don't have any particular ideas here how to fix it. My thought was "let the backends expand into the easiest code as possible and then clean it up with a generic pass", but I'm definitely open to different ideas.

> - This is a generic codegen pass but the description here indicates it only ever happens to match the patterns on PowerPC?

It's not so much that as the original patch was on by default and required changes to the ARM testcases, but the motivating example was particularly poor code on Power. We could probably throw some extra tests in, but it seems like a stretch to make all of the examples quite so universal? The code itself, of course, has no backend dependencies or even TTI.

Thoughts?

-eric


Repository:
  rL LLVM

https://reviews.llvm.org/D28249