[PATCH] D31944: [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)

[Sanjay Patel via Phabricator via llvm-commits]

spatel added a comment.

In https://reviews.llvm.org/D31944#738386, @efriedma wrote:

> > I was expecting ARM to match to 'vbic'
>
> For sext_inc_vec?  It's doing the xor in the wrong width for it to match.  Try changing the return type of sext_inc_vec to `<4 x i64>`, and you'll see essentially the same thing on AVX2.


Ah, my NEON literacy is even worse than my SSE. I overlooked the differing widths.


https://reviews.llvm.org/D31944