[llvm] r301404 - Fix signed multiplication with overflow fallback.

[Ranjeet Singh via llvm-commits]

Author: rsingh
Date: Wed Apr 26 08:41:43 2017
New Revision: 301404

URL: http://llvm.org/viewvc/llvm-project?rev=301404&view=rev
Log:
Fix signed multiplication with overflow fallback.

For targets that don't have ISD::MULHS or ISD::SMUL_LOHI for the type
and the double width type is illegal, then the two operands are
sign extended to twice their size then multiplied to check for overflow.
The extended upper halves were mismatched causing an incorrect result.
This fixes the mismatch.

A test was added for ARM V6-M where the bug was detected.

Patch by James Duley.

Differential Revision: https://reviews.llvm.org/D31807


Added:
    llvm/trunk/test/CodeGen/ARM/v6m-smul-with-overflow.ll
Modified:
    llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp

Modified: llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp?rev=301404&r1=301403&r2=301404&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp Wed Apr 26 08:41:43 2017
@@ -3497,11 +3497,11 @@ bool SelectionDAGLegalize::ExpandNode(SD
       // part.
       unsigned LoSize = VT.getSizeInBits();
       SDValue HiLHS =
-          DAG.getNode(ISD::SRA, dl, VT, RHS,
+          DAG.getNode(ISD::SRA, dl, VT, LHS,
                       DAG.getConstant(LoSize - 1, dl,
                                       TLI.getPointerTy(DAG.getDataLayout())));
       SDValue HiRHS =
-          DAG.getNode(ISD::SRA, dl, VT, LHS,
+          DAG.getNode(ISD::SRA, dl, VT, RHS,
                       DAG.getConstant(LoSize - 1, dl,
                                       TLI.getPointerTy(DAG.getDataLayout())));
 

Added: llvm/trunk/test/CodeGen/ARM/v6m-smul-with-overflow.ll
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/test/CodeGen/ARM/v6m-smul-with-overflow.ll?rev=301404&view=auto
==============================================================================
--- llvm/trunk/test/CodeGen/ARM/v6m-smul-with-overflow.ll (added)
+++ llvm/trunk/test/CodeGen/ARM/v6m-smul-with-overflow.ll Wed Apr 26 08:41:43 2017
@@ -0,0 +1,16 @@
+; RUN: llc < %s -mtriple=thumbv6m-none-eabi | FileCheck %s
+
+define i1 @signed_multiplication_did_overflow(i32, i32) {
+; CHECK-LABEL: signed_multiplication_did_overflow:
+entry-block:
+  %2 = tail call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %0, i32 %1)
+  %3 = extractvalue { i32, i1 } %2, 1
+  ret i1 %3
+
+; CHECK: mov    r2, r1
+; CHECK: asrs   r1, r0, #31
+; CHECK: asrs   r3, r2, #31
+; CHECK: bl     __aeabi_lmul
+}
+
+declare { i32, i1 } @llvm.smul.with.overflow.i32(i32, i32)