[PATCH] D32287: [X86] Add missing mayLoad/mayStore attributes to some X86 instructions (Continue)

[Ayman Musa via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rL301393: [X86] Add missing mayLoad/mayStore attributes to some X86 instructions… (authored by aymanmus).

Changed prior to commit:
  https://reviews.llvm.org/D32287?vs=95935&id=96714#toc

Repository:
  rL LLVM

https://reviews.llvm.org/D32287

Files:
  llvm/trunk/lib/Target/X86/X86InstrArithmetic.td


Index: llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
===================================================================
--- llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
+++ llvm/trunk/lib/Target/X86/X86InstrArithmetic.td
@@ -989,10 +989,12 @@
       }
     } // Constraints = "$src1 = $dst"
 
-    def NAME#8mr    : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
-    def NAME#16mr   : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
-    def NAME#32mr   : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
-    def NAME#64mr   : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
+    let mayLoad = 1, mayStore = 1 in {
+      def NAME#8mr    : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>;
+      def NAME#16mr   : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>;
+      def NAME#32mr   : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>;
+      def NAME#64mr   : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>;
+    }
 
     // NOTE: These are order specific, we want the mi8 forms to be listed
     // first so that they are slightly preferred to the mi forms.


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