[PATCH] D31944: [DAGCombiner] add (sext i1 X), 1 --> zext (not i1 X)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added a comment.

I'm not sure your description is the full story about the ARM code for cmpgt_sext_inc_vec; it looks like the following gets simplified for AVX2 (might want to include this as a testcase):

  define <4 x i64> @cmpgt_sext_inc_vec(<4 x i64> %x, <4 x i64> %y) {
    %cmp = icmp sgt <4 x i64> %x, %y
    %ext = sext <4 x i1> %cmp to <4 x i64>
    %add = add <4 x i64> %ext, <i64 1, i64 1, i64 1, i64 1>
    ret <4 x i64> %add
  }



---

A testcase for something like "((a != b) & (c != d)) + 1" might also be interesting.


https://reviews.llvm.org/D31944