[PATCH] D32277: Replace slow LEA instructions in X86
Simon Pilgrim via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 25 03:14:57 PDT 2017
RKSimon added a comment.
In https://reviews.llvm.org/D32277#736509, @lsaba wrote:
> In https://reviews.llvm.org/D32277#735719, @RKSimon wrote:
>
> > https://reviews.llvm.org/D32352 is looking at more aggressive conversion of IMUL to multiple LEA instructions.
>
>
> Thanks for notifying, the patch does not contain any 3-Operand LEAs as far as I can see, the only case we need to be careful with is for 2-Operand LEA with RBP/R13/EBP as a base register, since this is determined only after RA, I am thinking it's better to let my patch fix those cases rather than preventing that patch from running on the problematic targets
Sorry for being pedantic about the naming, but for AMD architectures the 'slowlea' cases (whether it uses the ALU or AGU pipe) include scale != 1 (even for 2-ops), but it doesn't seem to be noticeably affected by RBP/R13/EBP. Hence my interest in PR32326 to try and make it easier to discriminate.
https://reviews.llvm.org/D32277
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