[PATCH] D32391: [SelectionDAG] Improve support for promotion of <1 x fX> floating point argument types (PR31008)

[Eli Friedman via Phabricator via llvm-commits]

efriedma added inline comments.


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Comment at: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:368
+    Val = ValueVT.isInteger() ? DAG.getAnyExtOrTrunc(Val, DL, ValueSVT)
+                              : DAG.getFPExtendOrRound(Val, DL, ValueSVT);
+  }
----------------
Is it actually possible for this to truncate/round?


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Comment at: lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:564
+      Val = PartVT.isInteger() ? DAG.getAnyExtOrTrunc(Val, DL, PartVT)
+                               : DAG.getFPExtendOrRound(Val, DL, PartVT);
     }
----------------
Unless I'm misreading this, we just set Val to an EXTRACT_VECTOR_ELT of type PartVT on the previous line; does this conversion do anything?


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Comment at: test/CodeGen/X86/pr31088.ll:14
+; SSE-NEXT:    movzwl %ax, %edi
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    movss %xmm0, (%rsp) # 4-byte Spill
----------------
This `__gnu_f2h_ieee` + `__gnu_h2f_ieee` sequence looks strange...


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Comment at: test/CodeGen/X86/pr31088.ll:21
+; SSE-NEXT:    callq __gnu_h2f_ieee
+; SSE-NEXT:    addss (%rsp), %xmm0 # 4-byte Folded Reload
+; SSE-NEXT:    popq %rax
----------------
Only tangentially related to your patch, but I'm not sure I understand the lowering here; addss is not a half-precision operation (and therefore won't produce correctly rounded results).


Repository:
  rL LLVM

https://reviews.llvm.org/D32391