[llvm] r301232 - Revert r301231: Accidentally committed stale files
Krzysztof Parzyszek via llvm-commits
llvm-commits at lists.llvm.org
Mon Apr 24 12:48:51 PDT 2017
Author: kparzysz
Date: Mon Apr 24 14:48:51 2017
New Revision: 301232
URL: http://llvm.org/viewvc/llvm-project?rev=301232&view=rev
Log:
Revert r301231: Accidentally committed stale files
I forgot to commit local changes before commit.
Modified:
llvm/trunk/include/llvm/Target/TargetLowering.h
llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp
llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp
llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
Modified: llvm/trunk/include/llvm/Target/TargetLowering.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetLowering.h?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetLowering.h (original)
+++ llvm/trunk/include/llvm/Target/TargetLowering.h Mon Apr 24 14:48:51 2017
@@ -2274,8 +2274,7 @@ protected:
/// Return true if the value types that can be represented by the specified
/// register class are all legal.
- bool isLegalRC(const TargetRegisterInfo &TRI,
- const TargetRegisterClass &RC) const;
+ bool isLegalRC(const TargetRegisterClass *RC) const;
/// Replace/modify any TargetFrameIndex operands with a targte-dependent
/// sequence of memory operands that is recognized by PrologEpilogInserter.
Modified: llvm/trunk/include/llvm/Target/TargetRegisterInfo.h
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/include/llvm/Target/TargetRegisterInfo.h?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/include/llvm/Target/TargetRegisterInfo.h (original)
+++ llvm/trunk/include/llvm/Target/TargetRegisterInfo.h Mon Apr 24 14:48:51 2017
@@ -40,12 +40,13 @@ class TargetRegisterClass {
public:
typedef const MCPhysReg* iterator;
typedef const MCPhysReg* const_iterator;
+ typedef const MVT::SimpleValueType* vt_iterator;
typedef const TargetRegisterClass* const * sc_iterator;
// Instance variables filled by tablegen, do not use!
const MCRegisterClass *MC;
const uint16_t SpillSize, SpillAlignment;
- const MVT::SimpleValueType *VTs;
+ const vt_iterator VTs;
const uint32_t *SubClassMask;
const uint16_t *SuperRegIndices;
const LaneBitmask LaneMask;
@@ -101,6 +102,26 @@ public:
/// registers.
bool isAllocatable() const { return MC->isAllocatable(); }
+ /// Return true if this TargetRegisterClass has the ValueType vt.
+ bool hasType(MVT vt) const {
+ for(int i = 0; VTs[i] != MVT::Other; ++i)
+ if (MVT(VTs[i]) == vt)
+ return true;
+ return false;
+ }
+
+ /// vt_begin / vt_end - Loop over all of the value types that can be
+ /// represented by values in this register class.
+ vt_iterator vt_begin() const {
+ return VTs;
+ }
+
+ vt_iterator vt_end() const {
+ vt_iterator I = VTs;
+ while (*I != MVT::Other) ++I;
+ return I;
+ }
+
/// Return true if the specified TargetRegisterClass
/// is a proper sub-class of this TargetRegisterClass.
bool hasSubClass(const TargetRegisterClass *RC) const {
@@ -218,7 +239,6 @@ struct RegClassWeight {
class TargetRegisterInfo : public MCRegisterInfo {
public:
typedef const TargetRegisterClass * const * regclass_iterator;
- typedef const MVT::SimpleValueType* vt_iterator;
private:
const TargetRegisterInfoDesc *InfoDesc; // Extra desc array for codegen
const char *const *SubRegIndexNames; // Names of subreg indexes.
@@ -317,27 +337,6 @@ public:
return RC.SpillAlignment;
}
- /// Return true if the given TargetRegisterClass has the ValueType T.
- bool hasType(const TargetRegisterClass &RC, MVT T) const {
- for (int i = 0; RC.VTs[i] != MVT::Other; ++i)
- if (MVT(RC.VTs[i]) == T)
- return true;
- return false;
- }
-
- /// Loop over all of the value types that can be represented by values
- // in the given register class.
- vt_iterator valuetypes_begin(const TargetRegisterClass &RC) const {
- return RC.VTs;
- }
-
- vt_iterator valuetypes_end(const TargetRegisterClass &RC) const {
- vt_iterator I = RC.VTs;
- while (*I != MVT::Other)
- ++I;
- return I;
- }
-
/// Returns the Register Class of a physical register of the given type,
/// picking the most sub register class of the right type that contains this
/// physreg.
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/InstrEmitter.cpp Mon Apr 24 14:48:51 2017
@@ -161,8 +161,7 @@ EmitCopyFromReg(SDNode *Node, unsigned R
if (VRBase) {
DstRC = MRI->getRegClass(VRBase);
} else if (UseRC) {
- assert(TRI->hasType(*UseRC, VT) &&
- "Incompatible phys register def and uses!");
+ assert(UseRC->hasType(VT) && "Incompatible phys register def and uses!");
DstRC = UseRC;
} else {
DstRC = TLI->getRegClassFor(VT);
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp Mon Apr 24 14:48:51 2017
@@ -6653,12 +6653,12 @@ static void GetRegistersForValue(Selecti
MachineFunction &MF = DAG.getMachineFunction();
SmallVector<unsigned, 4> Regs;
- const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
// If this is a constraint for a single physreg, or a constraint for a
// register class, find it.
std::pair<unsigned, const TargetRegisterClass *> PhysReg =
- TLI.getRegForInlineAsmConstraint(&TRI, OpInfo.ConstraintCode,
+ TLI.getRegForInlineAsmConstraint(MF.getSubtarget().getRegisterInfo(),
+ OpInfo.ConstraintCode,
OpInfo.ConstraintVT);
unsigned NumRegs = 1;
@@ -6667,11 +6667,11 @@ static void GetRegistersForValue(Selecti
// cast of the input value. More generally, handle any case where the input
// value disagrees with the register class we plan to stick this in.
if (OpInfo.Type == InlineAsm::isInput &&
- PhysReg.second && !TRI.hasType(*PhysReg.second, OpInfo.ConstraintVT)) {
+ PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
// Try to convert to the first EVT that the reg class contains. If the
// types are identical size, use a bitcast to convert (e.g. two differing
// vector types).
- MVT RegVT = *TRI.valuetypes_begin(*PhysReg.second);
+ MVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.CallOperand.getValueSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL,
RegVT, OpInfo.CallOperand);
@@ -6699,12 +6699,12 @@ static void GetRegistersForValue(Selecti
if (unsigned AssignedReg = PhysReg.first) {
const TargetRegisterClass *RC = PhysReg.second;
if (OpInfo.ConstraintVT == MVT::Other)
- ValueVT = *TRI.valuetypes_begin(*RC);
+ ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user
// may have asked for (e.g.) the AX register in i32 type. We need to
// remember that AX is actually i16 to get the right extension.
- RegVT = *TRI.valuetypes_begin(*RC);
+ RegVT = *RC->vt_begin();
// This is a explicit reference to a physical register.
Regs.push_back(AssignedReg);
@@ -6730,7 +6730,7 @@ static void GetRegistersForValue(Selecti
// Otherwise, if this was a reference to an LLVM register class, create vregs
// for this reference.
if (const TargetRegisterClass *RC = PhysReg.second) {
- RegVT = *TRI.valuetypes_begin(*RC);
+ RegVT = *RC->vt_begin();
if (OpInfo.ConstraintVT == MVT::Other)
ValueVT = RegVT;
Modified: llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp (original)
+++ llvm/trunk/lib/CodeGen/SelectionDAG/TargetLowering.cpp Mon Apr 24 14:48:51 2017
@@ -2541,7 +2541,7 @@ TargetLowering::getRegForInlineAsmConstr
for (const TargetRegisterClass *RC : RI->regclasses()) {
// If none of the value types for this register class are valid, we
// can't use it. For example, 64-bit reg classes on 32-bit targets.
- if (!isLegalRC(*RI, *RC))
+ if (!isLegalRC(RC))
continue;
for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
@@ -2553,9 +2553,9 @@ TargetLowering::getRegForInlineAsmConstr
// If this register class has the requested value type, return it,
// otherwise keep searching and return the first class found
// if no other is found which explicitly has the requested type.
- if (RI->hasType(*RC, VT))
+ if (RC->hasType(VT))
return S;
- if (!R.second)
+ else if (!R.second)
R = S;
}
}
Modified: llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetLoweringBase.cpp Mon Apr 24 14:48:51 2017
@@ -1184,11 +1184,12 @@ static unsigned getVectorTypeBreakdownMV
/// isLegalRC - Return true if the value types that can be represented by the
/// specified register class are all legal.
-bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
- const TargetRegisterClass &RC) const {
- for (auto I = TRI.valuetypes_begin(RC); *I != MVT::Other; ++I)
+bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
+ for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
+ I != E; ++I) {
if (isTypeLegal(*I))
return true;
+ }
return false;
}
@@ -1300,7 +1301,7 @@ TargetLoweringBase::findRepresentativeCl
// We want the largest possible spill size.
if (TRI->getSpillSize(*SuperRC) <= TRI->getSpillSize(*BestRC))
continue;
- if (!isLegalRC(*TRI, *SuperRC))
+ if (!isLegalRC(SuperRC))
continue;
BestRC = SuperRC;
}
Modified: llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp (original)
+++ llvm/trunk/lib/CodeGen/TargetRegisterInfo.cpp Mon Apr 24 14:48:51 2017
@@ -156,7 +156,7 @@ TargetRegisterInfo::getMinimalPhysRegCla
// this physreg.
const TargetRegisterClass* BestRC = nullptr;
for (const TargetRegisterClass* RC : regclasses()) {
- if ((VT == MVT::Other || hasType(*RC, VT)) && RC->contains(reg) &&
+ if ((VT == MVT::Other || RC->hasType(VT)) && RC->contains(reg) &&
(!BestRC || BestRC->hasSubClass(RC)))
BestRC = RC;
}
@@ -207,7 +207,7 @@ const TargetRegisterClass *firstCommonCl
if (unsigned Common = *A++ & *B++) {
const TargetRegisterClass *RC =
TRI->getRegClass(I + countTrailingZeros(Common));
- if (SVT == MVT::SimpleValueType::Any || TRI->hasType(*RC, VT))
+ if (SVT == MVT::SimpleValueType::Any || RC->hasType(VT))
return RC;
}
return nullptr;
Modified: llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRInstrInfo.cpp Mon Apr 24 14:48:51 2017
@@ -142,9 +142,9 @@ void AVRInstrInfo::storeRegToStackSlot(M
MFI.getObjectAlignment(FrameIndex));
unsigned Opcode = 0;
- if (TRI->hasType(*RC, MVT::i8)) {
+ if (RC->hasType(MVT::i8)) {
Opcode = AVR::STDPtrQRr;
- } else if (TRI->hasType(*RC, MVT::i16)) {
+ } else if (RC->hasType(MVT::i16)) {
Opcode = AVR::STDWPtrQRr;
} else {
llvm_unreachable("Cannot store this register into a stack slot!");
@@ -176,9 +176,9 @@ void AVRInstrInfo::loadRegFromStackSlot(
MFI.getObjectAlignment(FrameIndex));
unsigned Opcode = 0;
- if (TRI->hasType(*RC, MVT::i8)) {
+ if (RC->hasType(MVT::i8)) {
Opcode = AVR::LDDRdPtrQ;
- } else if (TRI->hasType(*RC, MVT::i16)) {
+ } else if (RC->hasType(MVT::i16)) {
// Opcode = AVR::LDDWRdPtrQ;
//:FIXME: remove this once PR13375 gets fixed
Opcode = AVR::LDDWRdYQ;
Modified: llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp (original)
+++ llvm/trunk/lib/Target/AVR/AVRRegisterInfo.cpp Mon Apr 24 14:48:51 2017
@@ -78,12 +78,11 @@ BitVector AVRRegisterInfo::getReservedRe
const TargetRegisterClass *
AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
const MachineFunction &MF) const {
- const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
- if (TRI->hasType(*RC, MVT::i16)) {
+ if (RC->hasType(MVT::i16)) {
return &AVR::DREGSRegClass;
}
- if (TRI->hasType(*RC, MVT::i8)) {
+ if (RC->hasType(MVT::i8)) {
return &AVR::GPR8RegClass;
}
Modified: llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsOptimizePICCall.cpp Mon Apr 24 14:48:51 2017
@@ -116,10 +116,9 @@ static MachineOperand *getCallTargetRegO
/// Return type of register Reg.
static MVT::SimpleValueType getRegTy(unsigned Reg, MachineFunction &MF) {
- const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
- assert(TRI.valuetypes_end(*RC) - TRI.valuetypes_begin(*RC) == 1);
- return *TRI.valuetypes_begin(*RC);
+ assert(RC->vt_end() - RC->vt_begin() == 1);
+ return *RC->vt_begin();
}
/// Do the following transformation:
Modified: llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/Mips/MipsSEInstrInfo.cpp Mon Apr 24 14:48:51 2017
@@ -207,13 +207,13 @@ storeRegToStack(MachineBasicBlock &MBB,
Opc = Mips::SDC1;
else if (Mips::FGR64RegClass.hasSubClassEq(RC))
Opc = Mips::SDC164;
- else if (TRI->hasType(*RC, MVT::v16i8))
+ else if (RC->hasType(MVT::v16i8))
Opc = Mips::ST_B;
- else if (TRI->hasType(*RC, MVT::v8i16) || TRI->hasType(*RC, MVT::v8f16))
+ else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
Opc = Mips::ST_H;
- else if (TRI->hasType(*RC, MVT::v4i32) || TRI->hasType(*RC, MVT::v4f32))
+ else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
Opc = Mips::ST_W;
- else if (TRI->hasType(*RC, MVT::v2i64) || TRI->hasType(*RC, MVT::v2f64))
+ else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
Opc = Mips::ST_D;
else if (Mips::LO32RegClass.hasSubClassEq(RC))
Opc = Mips::SW;
@@ -280,13 +280,13 @@ loadRegFromStack(MachineBasicBlock &MBB,
Opc = Mips::LDC1;
else if (Mips::FGR64RegClass.hasSubClassEq(RC))
Opc = Mips::LDC164;
- else if (TRI->hasType(*RC, MVT::v16i8))
+ else if (RC->hasType(MVT::v16i8))
Opc = Mips::LD_B;
- else if (TRI->hasType(*RC, MVT::v8i16) || TRI->hasType(*RC, MVT::v8f16))
+ else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
Opc = Mips::LD_H;
- else if (TRI->hasType(*RC, MVT::v4i32) || TRI->hasType(*RC, MVT::v4f32))
+ else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
Opc = Mips::LD_W;
- else if (TRI->hasType(*RC, MVT::v2i64) || TRI->hasType(*RC, MVT::v2f64))
+ else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
Opc = Mips::LD_D;
else if (Mips::HI32RegClass.hasSubClassEq(RC))
Opc = Mips::LW;
Modified: llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/PowerPC/PPCISelLowering.cpp Mon Apr 24 14:48:51 2017
@@ -9057,7 +9057,6 @@ PPCTargetLowering::emitEHSjLjSetJmp(Mach
MachineBasicBlock *MBB) const {
DebugLoc DL = MI.getDebugLoc();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
- const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
MachineFunction *MF = MBB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -9071,7 +9070,7 @@ PPCTargetLowering::emitEHSjLjSetJmp(Mach
unsigned DstReg = MI.getOperand(0).getReg();
const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
- assert(TRI->hasType(*RC, MVT::i32) && "Invalid destination!");
+ assert(RC->hasType(MVT::i32) && "Invalid destination!");
unsigned mainDstReg = MRI.createVirtualRegister(RC);
unsigned restoreDstReg = MRI.createVirtualRegister(RC);
@@ -9154,6 +9153,7 @@ PPCTargetLowering::emitEHSjLjSetJmp(Mach
// Setup
MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
+ const PPCRegisterInfo *TRI = Subtarget.getRegisterInfo();
MIB.addRegMask(TRI->getNoPreservedMask());
BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
Modified: llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/Sparc/SparcISelLowering.cpp Mon Apr 24 14:48:51 2017
@@ -3234,7 +3234,6 @@ SparcTargetLowering::emitEHSjLjSetJmp(Ma
MachineBasicBlock *MBB) const {
DebugLoc DL = MI.getDebugLoc();
const TargetInstrInfo *TII = Subtarget->getInstrInfo();
- const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
MachineFunction *MF = MBB->getParent();
MachineRegisterInfo &MRI = MF->getRegInfo();
@@ -3246,8 +3245,7 @@ SparcTargetLowering::emitEHSjLjSetJmp(Ma
unsigned DstReg = MI.getOperand(0).getReg();
const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
- assert(TRI->hasType(*RC, MVT::i32) && "Invalid destination!");
- (void)TRI;
+ assert(RC->hasType(MVT::i32) && "Invalid destination!");
unsigned mainDstReg = MRI.createVirtualRegister(RC);
unsigned restoreDstReg = MRI.createVirtualRegister(RC);
Modified: llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp (original)
+++ llvm/trunk/lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp Mon Apr 24 14:48:51 2017
@@ -45,11 +45,10 @@ using namespace llvm;
//===----------------------------------------------------------------------===//
MVT WebAssemblyAsmPrinter::getRegType(unsigned RegNo) const {
- const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
for (MVT T : {MVT::i32, MVT::i64, MVT::f32, MVT::f64, MVT::v16i8, MVT::v8i16,
MVT::v4i32, MVT::v4f32})
- if (TRI->hasType(*TRC, T))
+ if (TRC->hasType(T))
return T;
DEBUG(errs() << "Unknown type for register number: " << RegNo);
llvm_unreachable("Unknown register type");
Modified: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86ISelLowering.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp Mon Apr 24 14:48:51 2017
@@ -25944,7 +25944,6 @@ X86TargetLowering::emitEHSjLjSetJmp(Mach
DebugLoc DL = MI.getDebugLoc();
MachineFunction *MF = MBB->getParent();
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
- const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
MachineRegisterInfo &MRI = MF->getRegInfo();
const BasicBlock *BB = MBB->getBasicBlock();
@@ -25961,8 +25960,7 @@ X86TargetLowering::emitEHSjLjSetJmp(Mach
DstReg = MI.getOperand(CurOp++).getReg();
const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
- assert(TRI->hasType(*RC, MVT::i32) && "Invalid destination!");
- (void)TRI;
+ assert(RC->hasType(MVT::i32) && "Invalid destination!");
unsigned mainDstReg = MRI.createVirtualRegister(RC);
unsigned restoreDstReg = MRI.createVirtualRegister(RC);
@@ -35939,7 +35937,7 @@ X86TargetLowering::getRegForInlineAsmCon
// type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to
// turn into {ax},{dx}.
// MVT::Other is used to specify clobber names.
- if (TRI->hasType(*Res.second, VT) || VT == MVT::Other)
+ if (Res.second->hasType(VT) || VT == MVT::Other)
return Res; // Correct type already, nothing to do.
// Get a matching integer of the correct size. i.e. "ax" with MVT::32 should
@@ -35977,11 +35975,11 @@ X86TargetLowering::getRegForInlineAsmCon
Res.second = &X86::FR32RegClass;
else if (VT == MVT::f64 || VT == MVT::i64)
Res.second = &X86::FR64RegClass;
- else if (TRI->hasType(X86::VR128RegClass, VT))
+ else if (X86::VR128RegClass.hasType(VT))
Res.second = &X86::VR128RegClass;
- else if (TRI->hasType(X86::VR256RegClass, VT))
+ else if (X86::VR256RegClass.hasType(VT))
Res.second = &X86::VR256RegClass;
- else if (TRI->hasType(X86::VR512RegClass, VT))
+ else if (X86::VR512RegClass.hasType(VT))
Res.second = &X86::VR512RegClass;
else {
// Type mismatch and not a clobber: Return an error;
Modified: llvm/trunk/lib/Target/X86/X86InstrInfo.cpp
URL: http://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/X86/X86InstrInfo.cpp?rev=301232&r1=301231&r2=301232&view=diff
==============================================================================
--- llvm/trunk/lib/Target/X86/X86InstrInfo.cpp (original)
+++ llvm/trunk/lib/Target/X86/X86InstrInfo.cpp Mon Apr 24 14:48:51 2017
@@ -8747,7 +8747,7 @@ X86InstrInfo::unfoldMemoryOperand(Select
// Emit the load instruction.
SDNode *Load = nullptr;
if (FoldedLoad) {
- EVT VT = *TRI.valuetypes_begin(*RC);
+ EVT VT = *RC->vt_begin();
std::pair<MachineInstr::mmo_iterator,
MachineInstr::mmo_iterator> MMOs =
MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
@@ -8775,7 +8775,7 @@ X86InstrInfo::unfoldMemoryOperand(Select
const TargetRegisterClass *DstRC = nullptr;
if (MCID.getNumDefs() > 0) {
DstRC = getRegClass(MCID, 0, &RI, MF);
- VTs.push_back(*TRI.valuetypes_begin(*DstRC));
+ VTs.push_back(*DstRC->vt_begin());
}
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
EVT VT = N->getValueType(i);
More information about the llvm-commits
mailing list